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0353-arm64-dts-qcom-Add-IPQ9574-PPE-base-device-node.patch

0353-arm64-dts-qcom-Add-IPQ9574-PPE-base-device-node.patch 2.3 KB
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  1. From bbf706ecfd4295d73c8217d5220573dd51d7a081 Mon Sep 17 00:00:00 2001
    2. 

  2. From: Luo Jie <[email protected]>
    3. 

  3. Date: Fri, 1 Mar 2024 14:46:45 +0800
    4. 

  4. Subject: [PATCH] arm64: dts: qcom: Add IPQ9574 PPE base device node
    5. 

  5. 

  6. PPE is the packet process engine on the Qualcomm IPQ platform,
    7. 

  7. which is connected with the external switch or PHY device via
    8. 

  8. the UNIPHY (PCS).
    9. 

  9. 

  10. Change-Id: I254bd48c218aa4eab54f697a2ad149f5a93b682c
    11. 

  11. Signed-off-by: Luo Jie <[email protected]>
    12. 

  12. Alex G: Add "qcom_ppe" label to PPE node
    13. 

  13. Signed-off-by: Alexandru Gagniuc <[email protected]>
    14. 

  14. ---
    15. 

  15.  arch/arm64/boot/dts/qcom/ipq9574.dtsi | 39 +++++++++++++++++++++++++++
    16. 

  16.  1 file changed, 39 insertions(+)
    17. 

  17. 

  18. --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
    19. 

  19. +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
    20. 

  20. @@ -13,6 +13,7 @@
    21. 

  21.  #include <dt-bindings/interconnect/qcom,ipq9574.h>
    22. 

  22.  #include <dt-bindings/interrupt-controller/arm-gic.h>
    23. 

  23.  #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
    24. 

  24. +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
    25. 

  25.  #include <dt-bindings/thermal/thermal.h>
    26. 

  26.  
    27. 

  27.  / {
    28. 

  28. @@ -1271,6 +1272,44 @@
    29. 

  29.  			#interconnect-cells = <1>;
    30. 

  30.  		};
    31. 

  31.  
    32. 

  32. +		qcom_ppe: ethernet@3a000000 {
    33. 

  33. +			compatible = "qcom,ipq9574-ppe";
    34. 

  34. +			reg = <0x3a000000 0xbef800>;
    35. 

  35. +			ranges;
    36. 

  36. +			#address-cells = <1>;
    37. 

  37. +			#size-cells = <1>;
    38. 

  38. +			clocks = <&nsscc NSS_CC_PPE_SWITCH_CLK>,
    39. 

  39. +				 <&nsscc NSS_CC_PPE_SWITCH_CFG_CLK>,
    40. 

  40. +				 <&nsscc NSS_CC_PPE_SWITCH_IPE_CLK>,
    41. 

  41. +				 <&nsscc NSS_CC_PPE_SWITCH_BTQ_CLK>;
    42. 

  42. +			clock-names = "ppe",
    43. 

  43. +				      "ppe_cfg",
    44. 

  44. +				      "ppe_ipe",
    45. 

  45. +				      "ppe_btq";
    46. 

  46. +			resets = <&nsscc PPE_FULL_RESET>;
    47. 

  47. +			interconnects = <&nsscc MASTER_NSSNOC_PPE
    48. 

  48. +					 &nsscc SLAVE_NSSNOC_PPE>,
    49. 

  49. +					<&nsscc MASTER_NSSNOC_PPE_CFG
    50. 

  50. +					 &nsscc SLAVE_NSSNOC_PPE_CFG>,
    51. 

  51. +					<&gcc MASTER_NSSNOC_QOSGEN_REF
    52. 

  52. +					 &gcc SLAVE_NSSNOC_QOSGEN_REF>,
    53. 

  53. +					<&gcc MASTER_NSSNOC_TIMEOUT_REF
    54. 

  54. +					 &gcc SLAVE_NSSNOC_TIMEOUT_REF>,
    55. 

  55. +					<&gcc MASTER_MEM_NOC_NSSNOC
    56. 

  56. +					 &gcc SLAVE_MEM_NOC_NSSNOC>,
    57. 

  57. +					<&gcc MASTER_NSSNOC_MEMNOC
    58. 

  58. +					 &gcc SLAVE_NSSNOC_MEMNOC>,
    59. 

  59. +					<&gcc MASTER_NSSNOC_MEM_NOC_1
    60. 

  60. +					 &gcc SLAVE_NSSNOC_MEM_NOC_1>;
    61. 

  61. +			interconnect-names = "ppe",
    62. 

  62. +					     "ppe_cfg",
    63. 

  63. +					     "qos_gen",
    64. 

  64. +					     "timeout_ref",
    65. 

  65. +					     "nssnoc_memnoc",
    66. 

  66. +					     "memnoc_nssnoc",
    67. 

  67. +					     "memnoc_nssnoc_1";
    68. 

  68. +		};
    69. 

  69. +
    70. 

  70.  		pcs_uniphy0: ethernet-pcs@7a00000 {
    71. 

  71.  			compatible = "qcom,ipq9574-pcs";
    72. 

  72.  			reg = <0x7a00000 0x10000>;
    73.