rtl839x.dtsi 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "macros.dtsi"
  3. #include <dt-bindings/clock/rtl83xx-clk.h>
  4. /dts-v1/;
  5. / {
  6. #address-cells = <1>;
  7. #size-cells = <1>;
  8. compatible = "realtek,rtl839x-soc";
  9. osc: oscillator {
  10. compatible = "fixed-clock";
  11. #clock-cells = <0>;
  12. clock-frequency = <25000000>;
  13. };
  14. ccu: clock-controller {
  15. compatible = "realtek,rtl8390-clock";
  16. #clock-cells = <1>;
  17. clocks = <&osc>;
  18. clock-names = "ref_clk";
  19. };
  20. cpus {
  21. #address-cells = <1>;
  22. #size-cells = <0>;
  23. cpu@0 {
  24. compatible = "mips,mips34Kc";
  25. reg = <0>;
  26. clocks = <&ccu CLK_CPU>;
  27. operating-points-v2 = <&cpu_opp_table>;
  28. };
  29. cpu@1 {
  30. compatible = "mips,mips34Kc";
  31. reg = <1>;
  32. clocks = <&ccu CLK_CPU>;
  33. operating-points-v2 = <&cpu_opp_table>;
  34. };
  35. };
  36. cpu_opp_table: opp-table-0 {
  37. compatible = "operating-points-v2";
  38. opp-shared;
  39. opp00 {
  40. opp-hz = /bits/ 64 <425000000>;
  41. };
  42. opp01 {
  43. opp-hz = /bits/ 64 <450000000>;
  44. };
  45. opp02 {
  46. opp-hz = /bits/ 64 <475000000>;
  47. };
  48. opp03 {
  49. opp-hz = /bits/ 64 <500000000>;
  50. };
  51. opp04 {
  52. opp-hz = /bits/ 64 <525000000>;
  53. };
  54. opp05 {
  55. opp-hz = /bits/ 64 <550000000>;
  56. };
  57. opp06 {
  58. opp-hz = /bits/ 64 <575000000>;
  59. };
  60. opp07 {
  61. opp-hz = /bits/ 64 <600000000>;
  62. };
  63. opp08 {
  64. opp-hz = /bits/ 64 <625000000>;
  65. };
  66. opp09 {
  67. opp-hz = /bits/ 64 <650000000>;
  68. };
  69. opp10 {
  70. opp-hz = /bits/ 64 <675000000>;
  71. };
  72. opp11 {
  73. opp-hz = /bits/ 64 <700000000>;
  74. };
  75. opp12 {
  76. opp-hz = /bits/ 64 <725000000>;
  77. };
  78. opp13 {
  79. opp-hz = /bits/ 64 <750000000>;
  80. };
  81. };
  82. aliases {
  83. serial0 = &uart0;
  84. serial1 = &uart1;
  85. };
  86. chosen {
  87. bootargs = "earlycon";
  88. stdout-path = "serial0:115200n8";
  89. };
  90. cpuintc: cpuintc {
  91. compatible = "mti,cpu-interrupt-controller";
  92. #address-cells = <0>;
  93. #interrupt-cells = <1>;
  94. interrupt-controller;
  95. };
  96. soc: soc {
  97. compatible = "simple-bus";
  98. #address-cells = <1>;
  99. #size-cells = <1>;
  100. ranges = <0x0 0x18000000 0x10000>;
  101. intc: interrupt-controller@3000 {
  102. compatible = "realtek,rtl8390-intc", "realtek,rtl-intc";
  103. reg = <0x3000 0x18>, <0x3018 0x18>;
  104. interrupt-controller;
  105. #interrupt-cells = <2>;
  106. interrupt-parent = <&cpuintc>;
  107. interrupts = <2>, <3>, <4>, <5>, <6>;
  108. };
  109. spi0: spi@1200 {
  110. compatible = "realtek,rtl8380-spi";
  111. reg = <0x1200 0x100>;
  112. #address-cells = <1>;
  113. #size-cells = <0>;
  114. };
  115. timer0: timer@3100 {
  116. compatible = "realtek,rtl8390-timer", "realtek,otto-timer";
  117. reg = <0x3100 0x10>, <0x3110 0x10>, <0x3120 0x10>,
  118. <0x3130 0x10>, <0x3140 0x10>;
  119. interrupt-parent = <&intc>;
  120. interrupts = <29 4>, <28 4>, <17 4>, <16 4>, <15 4>;
  121. clocks = <&ccu CLK_LXB>;
  122. };
  123. uart0: uart@2000 {
  124. compatible = "ns16550a";
  125. reg = <0x2000 0x100>;
  126. clocks = <&ccu CLK_LXB>;
  127. interrupt-parent = <&intc>;
  128. interrupts = <31 1>;
  129. reg-io-width = <1>;
  130. reg-shift = <2>;
  131. fifo-size = <1>;
  132. no-loopback-test;
  133. };
  134. uart1: uart@2100 {
  135. pinctrl-names = "default";
  136. pinctrl-0 = <&enable_uart1>;
  137. compatible = "ns16550a";
  138. reg = <0x2100 0x100>;
  139. clocks = <&ccu CLK_LXB>;
  140. interrupt-parent = <&intc>;
  141. interrupts = <30 2>;
  142. reg-io-width = <1>;
  143. reg-shift = <2>;
  144. fifo-size = <1>;
  145. no-loopback-test;
  146. status = "disabled";
  147. };
  148. gpio0: gpio-controller@3500 {
  149. compatible = "realtek,rtl8390-gpio", "realtek,otto-gpio";
  150. reg = <0x3500 0x20>;
  151. gpio-controller;
  152. #gpio-cells = <2>;
  153. ngpios = <24>;
  154. interrupt-controller;
  155. #interrupt-cells = <2>;
  156. interrupt-parent = <&intc>;
  157. interrupts = <23 2>;
  158. };
  159. watchdog0: watchdog@3150 {
  160. compatible = "realtek,rtl8390-wdt";
  161. reg = <0x3150 0xc>;
  162. realtek,reset-mode = "soc";
  163. clocks = <&ccu CLK_LXB>;
  164. timeout-sec = <30>;
  165. interrupt-parent = <&intc>;
  166. interrupt-names = "phase1", "phase2";
  167. interrupts = <19 4>, <18 4>;
  168. };
  169. };
  170. switchcore@1b000000 {
  171. compatible = "syscon", "simple-mfd";
  172. reg = <0x1b000000 0x10000>;
  173. #address-cells = <1>;
  174. #size-cells = <1>;
  175. mdio_ctrl: mdio-controller {
  176. compatible = "realtek,rtl8392-mdio", "realtek,otto-mdio";
  177. #address-cells = <1>;
  178. #size-cells = <0>;
  179. mdio_bus0: mdio-bus@0 {
  180. reg = <0>;
  181. #address-cells = <1>;
  182. #size-cells = <0>;
  183. };
  184. };
  185. mdio_aux: mdio-aux {
  186. compatible = "realtek,rtl8390-aux-mdio";
  187. #address-cells = <1>;
  188. #size-cells = <0>;
  189. status = "disabled";
  190. pinctrl-names = "default";
  191. pinctrl-0 = <&mdio_aux_mdx>;
  192. };
  193. mdio_serdes: mdio-serdes {
  194. compatible = "realtek,rtl8392-serdes-mdio", "realtek,otto-serdes-mdio";
  195. };
  196. pcs {
  197. compatible = "realtek,rtl8392-pcs", "realtek,otto-pcs";
  198. #address-cells = <1>;
  199. #size-cells = <0>;
  200. serdes0: serdes@0 {
  201. reg = <0>;
  202. };
  203. serdes1: serdes@1 {
  204. reg = <1>;
  205. };
  206. serdes2: serdes@2 {
  207. reg = <2>;
  208. };
  209. serdes3: serdes@3 {
  210. reg = <3>;
  211. };
  212. serdes4: serdes@4 {
  213. reg = <4>;
  214. };
  215. serdes5: serdes@5 {
  216. reg = <5>;
  217. };
  218. serdes6: serdes@6 {
  219. reg = <6>;
  220. };
  221. serdes7: serdes@7 {
  222. reg = <7>;
  223. };
  224. serdes8: serdes@8 {
  225. reg = <8>;
  226. };
  227. serdes9: serdes@9 {
  228. reg = <9>;
  229. };
  230. serdes10: serdes@10 {
  231. reg = <10>;
  232. };
  233. serdes11: serdes@11 {
  234. reg = <11>;
  235. };
  236. serdes12: serdes@12 {
  237. reg = <12>;
  238. };
  239. serdes13: serdes@13 {
  240. reg = <13>;
  241. };
  242. };
  243. soc_thermal: thermal {
  244. compatible = "realtek,rtl8390-thermal";
  245. #thermal-sensor-cells = <0>;
  246. };
  247. };
  248. pinmux@1b000004 {
  249. compatible = "pinctrl-single";
  250. reg = <0x1b000004 0x4>;
  251. pinctrl-single,bit-per-mux;
  252. pinctrl-single,register-width = <32>;
  253. pinctrl-single,function-mask = <0x1>;
  254. #pinctrl-cells = <2>;
  255. enable_uart1: pinmux_enable_uart1 {
  256. pinctrl-single,bits = <0x0 0x1 0x3>;
  257. };
  258. disable_jtag: pinmux_disable_jtag {
  259. pinctrl-single,bits = <0x0 0x2 0x3>;
  260. };
  261. };
  262. /* LED_GLB_CTRL */
  263. pinmux@1b0000e4 {
  264. compatible = "pinctrl-single";
  265. reg = <0x1b0000e4 0x4>;
  266. pinctrl-single,bit-per-mux;
  267. pinctrl-single,register-width = <32>;
  268. pinctrl-single,function-mask = <0x1>;
  269. #pinctrl-cells = <2>;
  270. /* enable GPIO 0 */
  271. pinmux_disable_sys_led: disable_sys_led {
  272. pinctrl-single,bits = <0x0 0x0 0x4000>;
  273. };
  274. /* enable AUX MDC/MDIO */
  275. mdio_aux_mdx: aux-mdx-pins {
  276. pinctrl-single,bits = <0x0 0x100000 0x1c0000>;
  277. };
  278. };
  279. ethernet0: ethernet@1b00a300 {
  280. compatible = "realtek,rtl838x-eth";
  281. reg = <0x1b00a300 0x100>;
  282. interrupt-parent = <&intc>;
  283. interrupts = <24 3>;
  284. phy-mode = "internal";
  285. fixed-link {
  286. speed = <1000>;
  287. full-duplex;
  288. };
  289. };
  290. sram0: sram@9f000000 {
  291. compatible = "mmio-sram";
  292. reg = <0x9f000000 0x18000>;
  293. #address-cells = <1>;
  294. #size-cells = <1>;
  295. ranges = <0 0x9f000000 0x18000>;
  296. };
  297. switch0: switch@1b000000 {
  298. status = "okay";
  299. compatible = "realtek,rtl83xx-switch";
  300. interrupt-parent = <&intc>;
  301. interrupts = <20 2>;
  302. };
  303. thermal_zones: thermal-zones {
  304. cpu-thermal {
  305. polling-delay-passive = <1000>;
  306. polling-delay = <1000>;
  307. coefficients = <1000 0>;
  308. thermal-sensors = <&soc_thermal>;
  309. trips {
  310. cpu-crit {
  311. temperature = <105000>;
  312. hysteresis = <2000>;
  313. type = "critical";
  314. };
  315. };
  316. };
  317. };
  318. };