075-v4.10-0002-net-phy-broadcom-Add-support-for-BCM54612E.patch 3.1 KB

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  1. From: Xo Wang <[email protected]>
  2. Date: Fri, 21 Oct 2016 10:20:13 -0700
  3. Subject: [PATCH] net: phy: broadcom: Add support for BCM54612E
  4. This PHY has internal delays enabled after reset. This clears the
  5. internal delay enables unless the interface specifically requests them.
  6. Signed-off-by: Xo Wang <[email protected]>
  7. Reviewed-by: Florian Fainelli <[email protected]>
  8. Reviewed-by: Joel Stanley <[email protected]>
  9. Signed-off-by: David S. Miller <[email protected]>
  10. ---
  11. --- a/drivers/net/phy/broadcom.c
  12. +++ b/drivers/net/phy/broadcom.c
  13. @@ -337,6 +337,41 @@ static int bcm5481_config_aneg(struct ph
  14. return ret;
  15. }
  16. +static int bcm54612e_config_aneg(struct phy_device *phydev)
  17. +{
  18. + int ret;
  19. +
  20. + /* First, auto-negotiate. */
  21. + ret = genphy_config_aneg(phydev);
  22. +
  23. + /* Clear TX internal delay unless requested. */
  24. + if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
  25. + (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {
  26. + /* Disable TXD to GTXCLK clock delay (default set) */
  27. + /* Bit 9 is the only field in shadow register 00011 */
  28. + bcm_phy_write_shadow(phydev, 0x03, 0);
  29. + }
  30. +
  31. + /* Clear RX internal delay unless requested. */
  32. + if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
  33. + (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
  34. + u16 reg;
  35. +
  36. + /* Errata: reads require filling in the write selector field */
  37. + bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
  38. + MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC);
  39. + reg = phy_read(phydev, MII_BCM54XX_AUX_CTL);
  40. + /* Disable RXD to RXC delay (default set) */
  41. + reg &= ~MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW;
  42. + /* Clear shadow selector field */
  43. + reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
  44. + bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
  45. + MII_BCM54XX_AUXCTL_MISC_WREN | reg);
  46. + }
  47. +
  48. + return ret;
  49. +}
  50. +
  51. static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
  52. {
  53. int val;
  54. @@ -485,6 +520,18 @@ static struct phy_driver broadcom_driver
  55. .ack_interrupt = bcm_phy_ack_intr,
  56. .config_intr = bcm_phy_config_intr,
  57. }, {
  58. + .phy_id = PHY_ID_BCM54612E,
  59. + .phy_id_mask = 0xfffffff0,
  60. + .name = "Broadcom BCM54612E",
  61. + .features = PHY_GBIT_FEATURES |
  62. + SUPPORTED_Pause | SUPPORTED_Asym_Pause,
  63. + .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
  64. + .config_init = bcm54xx_config_init,
  65. + .config_aneg = bcm54612e_config_aneg,
  66. + .read_status = genphy_read_status,
  67. + .ack_interrupt = bcm_phy_ack_intr,
  68. + .config_intr = bcm_phy_config_intr,
  69. +}, {
  70. .phy_id = PHY_ID_BCM54616S,
  71. .phy_id_mask = 0xfffffff0,
  72. .name = "Broadcom BCM54616S",
  73. @@ -600,6 +647,7 @@ static struct mdio_device_id __maybe_unu
  74. { PHY_ID_BCM5411, 0xfffffff0 },
  75. { PHY_ID_BCM5421, 0xfffffff0 },
  76. { PHY_ID_BCM5461, 0xfffffff0 },
  77. + { PHY_ID_BCM54612E, 0xfffffff0 },
  78. { PHY_ID_BCM54616S, 0xfffffff0 },
  79. { PHY_ID_BCM5464, 0xfffffff0 },
  80. { PHY_ID_BCM5481, 0xfffffff0 },
  81. --- a/include/linux/brcmphy.h
  82. +++ b/include/linux/brcmphy.h
  83. @@ -18,6 +18,7 @@
  84. #define PHY_ID_BCM5421 0x002060e0
  85. #define PHY_ID_BCM5464 0x002060b0
  86. #define PHY_ID_BCM5461 0x002060c0
  87. +#define PHY_ID_BCM54612E 0x03625e60
  88. #define PHY_ID_BCM54616S 0x03625d10
  89. #define PHY_ID_BCM57780 0x03625d90