qcom-ipq8064-r7500.dts 5.1 KB

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  1. #include "qcom-ipq8064-v1.0.dtsi"
  2. #include <dt-bindings/input/input.h>
  3. #include <dt-bindings/soc/qcom,tcsr.h>
  4. / {
  5. model = "Netgear Nighthawk X4 R7500";
  6. compatible = "netgear,r7500", "qcom,ipq8064";
  7. memory@0 {
  8. reg = <0x42000000 0xe000000>;
  9. device_type = "memory";
  10. };
  11. reserved-memory {
  12. #address-cells = <1>;
  13. #size-cells = <1>;
  14. ranges;
  15. rsvd@41200000 {
  16. reg = <0x41200000 0x300000>;
  17. no-map;
  18. };
  19. };
  20. aliases {
  21. mdio-gpio0 = &mdio0;
  22. led-boot = &power_white;
  23. led-failsafe = &power_amber;
  24. led-running = &power_white;
  25. led-upgrade = &power_amber;
  26. };
  27. chosen {
  28. bootargs = "rootfstype=squashfs noinitrd";
  29. };
  30. keys {
  31. compatible = "gpio-keys";
  32. pinctrl-0 = <&button_pins>;
  33. pinctrl-names = "default";
  34. wifi {
  35. label = "wifi";
  36. gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
  37. linux,code = <KEY_RFKILL>;
  38. debounce-interval = <60>;
  39. wakeup-source;
  40. };
  41. reset {
  42. label = "reset";
  43. gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
  44. linux,code = <KEY_RESTART>;
  45. debounce-interval = <60>;
  46. wakeup-source;
  47. };
  48. wps {
  49. label = "wps";
  50. gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
  51. linux,code = <KEY_WPS_BUTTON>;
  52. debounce-interval = <60>;
  53. wakeup-source;
  54. };
  55. };
  56. leds {
  57. compatible = "gpio-leds";
  58. pinctrl-0 = <&led_pins>;
  59. pinctrl-names = "default";
  60. usb1 {
  61. label = "white:usb1";
  62. gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
  63. };
  64. usb2 {
  65. label = "white:usb2";
  66. gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
  67. };
  68. power_amber: power_amber {
  69. label = "amber:power";
  70. gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
  71. };
  72. wan_white {
  73. label = "white:wan";
  74. gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
  75. };
  76. wan_amber {
  77. label = "amber:wan";
  78. gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
  79. };
  80. wps {
  81. label = "white:wps";
  82. gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
  83. };
  84. esata {
  85. label = "white:esata";
  86. gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
  87. };
  88. power_white: power_white {
  89. label = "white:power";
  90. gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
  91. default-state = "keep";
  92. };
  93. wifi {
  94. label = "white:wifi";
  95. gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
  96. };
  97. };
  98. };
  99. &qcom_pinmux {
  100. button_pins: button_pins {
  101. mux {
  102. pins = "gpio6", "gpio54", "gpio65";
  103. function = "gpio";
  104. drive-strength = <2>;
  105. bias-pull-up;
  106. };
  107. };
  108. led_pins: led_pins {
  109. mux {
  110. pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
  111. "gpio24","gpio26", "gpio53", "gpio64";
  112. function = "gpio";
  113. drive-strength = <2>;
  114. bias-pull-up;
  115. };
  116. };
  117. };
  118. &gsbi5 {
  119. status = "disabled";
  120. spi@1a280000 {
  121. status = "disabled";
  122. };
  123. };
  124. &usb3_0 {
  125. clocks = <&gcc USB30_1_MASTER_CLK>;
  126. status = "okay";
  127. };
  128. &usb3_1 {
  129. clocks = <&gcc USB30_0_MASTER_CLK>;
  130. status = "okay";
  131. };
  132. &pcie0 {
  133. status = "okay";
  134. };
  135. &pcie1 {
  136. status = "okay";
  137. max-link-speed = <1>;
  138. };
  139. &nand_controller {
  140. status = "okay";
  141. pinctrl-0 = <&nand_pins>;
  142. pinctrl-names = "default";
  143. nand@0 {
  144. reg = <0>;
  145. compatible = "qcom,nandcs";
  146. nand-ecc-strength = <4>;
  147. nand-bus-width = <8>;
  148. nand-ecc-step-size = <512>;
  149. nand-is-boot-medium;
  150. qcom,boot_pages_size = <0x1180000>;
  151. partitions {
  152. compatible = "fixed-partitions";
  153. #address-cells = <1>;
  154. #size-cells = <1>;
  155. qcadata@0 {
  156. label = "qcadata";
  157. reg = <0x0000000 0x0c80000>;
  158. read-only;
  159. };
  160. APPSBL@c80000 {
  161. label = "APPSBL";
  162. reg = <0x0c80000 0x0500000>;
  163. read-only;
  164. };
  165. APPSBLENV@1180000 {
  166. label = "APPSBLENV";
  167. reg = <0x1180000 0x0080000>;
  168. read-only;
  169. };
  170. art: art@1200000 {
  171. label = "art";
  172. reg = <0x1200000 0x0140000>;
  173. read-only;
  174. };
  175. kernel@1340000 {
  176. label = "kernel";
  177. reg = <0x1340000 0x0400000>;
  178. };
  179. ubi@1740000 {
  180. label = "ubi";
  181. reg = <0x1740000 0x1600000>;
  182. };
  183. netgear@2d40000 {
  184. label = "netgear";
  185. reg = <0x2d40000 0x0c00000>;
  186. read-only;
  187. };
  188. reserve@3940000 {
  189. label = "reserve";
  190. reg = <0x3940000 0x46c0000>;
  191. read-only;
  192. };
  193. };
  194. };
  195. };
  196. &mdio0 {
  197. status = "okay";
  198. pinctrl-0 = <&mdio0_pins>;
  199. pinctrl-names = "default";
  200. phy0: ethernet-phy@0 {
  201. reg = <0>;
  202. qca,ar8327-initvals = <
  203. 0x00004 0x7600000 /* PAD0_MODE */
  204. 0x00008 0x1000000 /* PAD5_MODE */
  205. 0x0000c 0x80 /* PAD6_MODE */
  206. 0x000e4 0x6a545 /* MAC_POWER_SEL */
  207. 0x000e0 0xc74164de /* SGMII_CTRL */
  208. 0x0007c 0x4e /* PORT0_STATUS */
  209. 0x00094 0x4e /* PORT6_STATUS */
  210. >;
  211. };
  212. phy4: ethernet-phy@4 {
  213. reg = <4>;
  214. };
  215. };
  216. &gmac1 {
  217. status = "okay";
  218. phy-mode = "rgmii";
  219. qcom,id = <1>;
  220. pinctrl-0 = <&rgmii2_pins>;
  221. pinctrl-names = "default";
  222. nvmem-cells = <&macaddr_art_6>;
  223. nvmem-cell-names = "mac-address";
  224. fixed-link {
  225. speed = <1000>;
  226. full-duplex;
  227. };
  228. };
  229. &gmac2 {
  230. status = "okay";
  231. phy-mode = "sgmii";
  232. qcom,id = <2>;
  233. nvmem-cells = <&macaddr_art_0>;
  234. nvmem-cell-names = "mac-address";
  235. fixed-link {
  236. speed = <1000>;
  237. full-duplex;
  238. };
  239. };
  240. &tcsr {
  241. qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
  242. compatible = "qcom,tcsr";
  243. };
  244. &adm_dma {
  245. status = "okay";
  246. };
  247. &art {
  248. compatible = "nvmem-cells";
  249. #address-cells = <1>;
  250. #size-cells = <1>;
  251. macaddr_art_0: macaddr@0 {
  252. reg = <0x0 0x6>;
  253. };
  254. macaddr_art_6: macaddr@6 {
  255. reg = <0x6 0x6>;
  256. };
  257. };