qcom-ipq8068-ecw5410.dts 5.1 KB

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  1. #include "qcom-ipq8064-v2.0.dtsi"
  2. #include <dt-bindings/input/input.h>
  3. #include <dt-bindings/soc/qcom,tcsr.h>
  4. / {
  5. model = "Edgecore ECW5410";
  6. compatible = "edgecore,ecw5410", "qcom,ipq8064";
  7. reserved-memory {
  8. nss@40000000 {
  9. reg = <0x40000000 0x1000000>;
  10. no-map;
  11. };
  12. smem: smem@41000000 {
  13. reg = <0x41000000 0x200000>;
  14. no-map;
  15. };
  16. wifi_dump@44000000 {
  17. reg = <0x44000000 0x600000>;
  18. no-map;
  19. };
  20. };
  21. cpus {
  22. idle-states {
  23. CPU_SPC: spc {
  24. status = "disabled";
  25. };
  26. };
  27. };
  28. aliases {
  29. serial1 = &gsbi1_serial;
  30. ethernet0 = &gmac2;
  31. ethernet1 = &gmac3;
  32. led-boot = &led_power_green;
  33. led-failsafe = &led_power_red;
  34. led-running = &led_power_green;
  35. led-upgrade = &led_power_green;
  36. };
  37. chosen {
  38. bootargs-append = " console=ttyMSM0,115200n8 root=/dev/ubiblock0_1";
  39. };
  40. keys {
  41. compatible = "gpio-keys";
  42. pinctrl-0 = <&button_pins>;
  43. pinctrl-names = "default";
  44. reset {
  45. label = "reset";
  46. gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>;
  47. linux,code = <KEY_RESTART>;
  48. debounce-interval = <60>;
  49. wakeup-source;
  50. };
  51. };
  52. leds {
  53. compatible = "gpio-leds";
  54. pinctrl-0 = <&led_pins>;
  55. pinctrl-names = "default";
  56. led_power_green: power_green {
  57. label = "green:power";
  58. gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;
  59. };
  60. wlan2g_green {
  61. label = "green:wlan2g";
  62. gpios = <&qcom_pinmux 23 GPIO_ACTIVE_LOW>;
  63. };
  64. wlan2g_yellow {
  65. label = "yellow:wlan2g";
  66. gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>;
  67. };
  68. wlan5g_green {
  69. label = "green:wlan5g";
  70. gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
  71. };
  72. led_power_red: power_red {
  73. label = "red:power";
  74. gpios = <&qcom_pinmux 28 GPIO_ACTIVE_LOW>;
  75. };
  76. wlan5g_yellow {
  77. label = "yellow:wlan5g";
  78. gpios = <&qcom_pinmux 59 GPIO_ACTIVE_LOW>;
  79. };
  80. };
  81. };
  82. &qcom_pinmux {
  83. spi_pins: spi_pins {
  84. mux {
  85. pins = "gpio18", "gpio19";
  86. function = "gsbi5";
  87. drive-strength = <10>;
  88. bias-pull-down;
  89. };
  90. clk {
  91. pins = "gpio21";
  92. function = "gsbi5";
  93. drive-strength = <12>;
  94. bias-pull-down;
  95. };
  96. cs {
  97. pins = "gpio20";
  98. function = "gpio";
  99. drive-strength = <10>;
  100. bias-pull-up;
  101. };
  102. };
  103. led_pins: led_pins {
  104. mux {
  105. pins = "gpio16", "gpio23", "gpio24", "gpio26",
  106. "gpio28", "gpio59";
  107. function = "gpio";
  108. drive-strength = <2>;
  109. bias-pull-up;
  110. };
  111. };
  112. button_pins: button_pins {
  113. mux {
  114. pins = "gpio25";
  115. function = "gpio";
  116. drive-strength = <2>;
  117. bias-pull-up;
  118. };
  119. };
  120. uart1_pins: uart1_pins {
  121. mux {
  122. pins = "gpio51", "gpio52", "gpio53", "gpio54";
  123. function = "gsbi1";
  124. drive-strength = <12>;
  125. bias-none;
  126. };
  127. };
  128. };
  129. &gsbi1 {
  130. qcom,mode = <GSBI_PROT_UART_W_FC>;
  131. status = "okay";
  132. serial@12450000 {
  133. status = "okay";
  134. pinctrl-0 = <&uart1_pins>;
  135. pinctrl-names = "default";
  136. };
  137. };
  138. &gsbi5 {
  139. qcom,mode = <GSBI_PROT_SPI>;
  140. status = "okay";
  141. spi4: spi@1a280000 {
  142. status = "okay";
  143. spi-max-frequency = <50000000>;
  144. pinctrl-0 = <&spi_pins>;
  145. pinctrl-names = "default";
  146. cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
  147. m25p80@0 {
  148. compatible = "jedec,spi-nor";
  149. #address-cells = <1>;
  150. #size-cells = <1>;
  151. spi-max-frequency = <50000000>;
  152. reg = <0>;
  153. partitions {
  154. compatible = "qcom,smem-part";
  155. };
  156. };
  157. };
  158. };
  159. &hs_phy_0 { /* USB3 port 0 HS phy */
  160. status = "okay";
  161. };
  162. &hs_phy_1 { /* USB3 port 1 HS phy */
  163. status = "okay";
  164. };
  165. &ss_phy_0 { /* USB3 port 0 SS phy */
  166. status = "okay";
  167. };
  168. &ss_phy_1 { /* USB3 port 1 SS phy */
  169. status = "okay";
  170. };
  171. &usb3_0 {
  172. status = "okay";
  173. };
  174. &usb3_1 {
  175. status = "okay";
  176. };
  177. &pcie1 {
  178. status = "okay";
  179. /delete-property/ pinctrl-0;
  180. /delete-property/ pinctrl-names;
  181. /delete-property/ perst-gpios;
  182. bridge@0,0 {
  183. reg = <0x00000000 0 0 0 0>;
  184. #address-cells = <3>;
  185. #size-cells = <2>;
  186. ranges;
  187. wifi@1,0 {
  188. compatible = "qcom,ath10k";
  189. status = "okay";
  190. reg = <0x00010000 0 0 0 0>;
  191. qcom,ath10k-calibration-variant = "Edgecore-ECW5410-L";
  192. };
  193. };
  194. };
  195. &pcie2 {
  196. status = "okay";
  197. /delete-property/ pinctrl-0;
  198. /delete-property/ pinctrl-names;
  199. /delete-property/ perst-gpios;
  200. bridge@0,0 {
  201. reg = <0x00000000 0 0 0 0>;
  202. #address-cells = <3>;
  203. #size-cells = <2>;
  204. ranges;
  205. wifi@1,0 {
  206. compatible = "qcom,ath10k";
  207. status = "okay";
  208. reg = <0x00010000 0 0 0 0>;
  209. qcom,ath10k-calibration-variant = "Edgecore-ECW5410-L";
  210. };
  211. };
  212. };
  213. &nand_controller {
  214. status = "okay";
  215. pinctrl-0 = <&nand_pins>;
  216. pinctrl-names = "default";
  217. nand@0 {
  218. compatible = "qcom,nandcs";
  219. reg = <0>;
  220. nand-ecc-strength = <4>;
  221. nand-bus-width = <8>;
  222. nand-ecc-step-size = <512>;
  223. partitions {
  224. compatible = "fixed-partitions";
  225. #address-cells = <1>;
  226. #size-cells = <1>;
  227. rootfs1@0 {
  228. label = "rootfs1";
  229. reg = <0x0000000 0x4000000>;
  230. };
  231. rootfs2@4000000 {
  232. label = "rootfs2";
  233. reg = <0x4000000 0x4000000>;
  234. };
  235. };
  236. };
  237. };
  238. &mdio0 {
  239. status = "okay";
  240. pinctrl-0 = <&mdio0_pins>;
  241. pinctrl-names = "default";
  242. phy0: ethernet-phy@0 {
  243. reg = <0>;
  244. };
  245. phy1: ethernet-phy@1 {
  246. reg = <1>;
  247. };
  248. };
  249. &gmac2 {
  250. status = "okay";
  251. qcom,id = <2>;
  252. mdiobus = <&mdio0>;
  253. phy-mode = "sgmii";
  254. phy-handle = <&phy1>;
  255. };
  256. &gmac3 {
  257. status = "okay";
  258. qcom,id = <3>;
  259. mdiobus = <&mdio0>;
  260. phy-mode = "sgmii";
  261. phy-handle = <&phy0>;
  262. };
  263. &adm_dma {
  264. status = "okay";
  265. };