mt7981b-xiaomi-mi-router-common.dtsi 3.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. /dts-v1/;
  3. #include <dt-bindings/input/input.h>
  4. #include <dt-bindings/gpio/gpio.h>
  5. #include "mt7981.dtsi"
  6. / {
  7. aliases {
  8. serial0 = &uart0;
  9. led-boot = &led_status_yellow;
  10. led-failsafe = &led_status_yellow;
  11. led-running = &led_status_blue;
  12. led-upgrade = &led_status_yellow;
  13. };
  14. chosen {
  15. stdout-path = "serial0:115200n8";
  16. };
  17. memory {
  18. reg = <0 0x40000000 0 0x10000000>;
  19. };
  20. gpio-keys {
  21. compatible = "gpio-keys";
  22. button-mesh {
  23. label = "mesh";
  24. gpios = <&pio 0 GPIO_ACTIVE_LOW>;
  25. linux,code = <BTN_9>;
  26. linux,input-type = <EV_SW>;
  27. };
  28. button-reset {
  29. label = "reset";
  30. gpios = <&pio 1 GPIO_ACTIVE_LOW>;
  31. linux,code = <KEY_RESTART>;
  32. };
  33. };
  34. leds: leds {
  35. compatible = "gpio-leds";
  36. led_status_blue: led-status-blue {
  37. color = <LED_COLOR_ID_BLUE>;
  38. function = LED_FUNCTION_STATUS;
  39. gpios = <&pio 9 GPIO_ACTIVE_LOW>;
  40. };
  41. led_status_yellow: led-status-yellow {
  42. color = <LED_COLOR_ID_YELLOW>;
  43. function = LED_FUNCTION_STATUS;
  44. gpios = <&pio 10 GPIO_ACTIVE_LOW>;
  45. };
  46. };
  47. };
  48. &eth {
  49. status = "okay";
  50. gmac0: mac@0 {
  51. compatible = "mediatek,eth-mac";
  52. reg = <0>;
  53. phy-mode = "2500base-x";
  54. fixed-link {
  55. speed = <2500>;
  56. full-duplex;
  57. pause;
  58. };
  59. };
  60. };
  61. &mdio_bus {
  62. switch: switch@1f {
  63. compatible = "mediatek,mt7531";
  64. reg = <31>;
  65. reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
  66. interrupt-controller;
  67. #interrupt-cells = <1>;
  68. interrupt-parent = <&pio>;
  69. interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
  70. };
  71. };
  72. &switch {
  73. ports {
  74. #address-cells = <1>;
  75. #size-cells = <0>;
  76. port@0 {
  77. reg = <0>;
  78. label = "wan";
  79. };
  80. port@1 {
  81. reg = <1>;
  82. label = "lan2";
  83. };
  84. port@2 {
  85. reg = <2>;
  86. label = "lan3";
  87. };
  88. port@3 {
  89. reg = <3>;
  90. label = "lan4";
  91. };
  92. port@6 {
  93. reg = <6>;
  94. ethernet = <&gmac0>;
  95. phy-mode = "2500base-x";
  96. fixed-link {
  97. speed = <2500>;
  98. full-duplex;
  99. pause;
  100. };
  101. };
  102. };
  103. };
  104. &spi0 {
  105. pinctrl-names = "default";
  106. pinctrl-0 = <&spi0_flash_pins>;
  107. status = "okay";
  108. spi_nand: flash@0 {
  109. #address-cells = <1>;
  110. #size-cells = <1>;
  111. compatible = "spi-nand";
  112. reg = <0>;
  113. spi-max-frequency = <52000000>;
  114. spi-tx-bus-width = <4>;
  115. spi-rx-bus-width = <4>;
  116. partitions: partitions {
  117. compatible = "fixed-partitions";
  118. #address-cells = <1>;
  119. #size-cells = <1>;
  120. partition@0 {
  121. label = "BL2";
  122. reg = <0x00 0x100000>;
  123. read-only;
  124. };
  125. partition@100000 {
  126. label = "Nvram";
  127. reg = <0x100000 0x40000>;
  128. };
  129. partition@140000 {
  130. label = "Bdata";
  131. reg = <0x140000 0x40000>;
  132. };
  133. factory: partition@180000 {
  134. label = "Factory";
  135. reg = <0x180000 0x200000>;
  136. read-only;
  137. nvmem-layout {
  138. compatible = "fixed-layout";
  139. #address-cells = <1>;
  140. #size-cells = <1>;
  141. eeprom_factory_0: eeprom@0 {
  142. reg = <0x0 0x1000>;
  143. };
  144. macaddr_factory_4: macaddr@4 {
  145. compatible = "mac-base";
  146. reg = <0x4 0x6>;
  147. #nvmem-cell-cells = <1>;
  148. };
  149. };
  150. };
  151. partition@380000 {
  152. label = "FIP";
  153. reg = <0x380000 0x200000>;
  154. read-only;
  155. };
  156. partition@580000 {
  157. label = "crash";
  158. reg = <0x580000 0x40000>;
  159. read-only;
  160. };
  161. partition@5c0000 {
  162. label = "crash_log";
  163. reg = <0x5c0000 0x40000>;
  164. read-only;
  165. };
  166. partition@7600000 {
  167. label = "KF";
  168. reg = <0x7600000 0x40000>;
  169. read-only;
  170. };
  171. };
  172. };
  173. };
  174. &pio {
  175. spi0_flash_pins: spi0-pins {
  176. mux {
  177. function = "spi";
  178. groups = "spi0", "spi0_wp_hold";
  179. };
  180. conf-pu {
  181. pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
  182. drive-strength = <MTK_DRIVE_8mA>;
  183. bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
  184. };
  185. conf-pd {
  186. pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
  187. drive-strength = <MTK_DRIVE_8mA>;
  188. bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
  189. };
  190. };
  191. };
  192. &wifi {
  193. status = "okay";
  194. nvmem-cells = <&eeprom_factory_0>;
  195. nvmem-cell-names = "eeprom";
  196. };
  197. &uart0 {
  198. status = "okay";
  199. };
  200. &watchdog {
  201. status = "okay";
  202. };