ramips.c 14 KB

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  1. /*
  2. * This program is free software; you can redistribute it and/or modify
  3. * it under the terms of the GNU General Public License as published by
  4. * the Free Software Foundation; version 2 of the License
  5. *
  6. * This program is distributed in the hope that it will be useful,
  7. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  8. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  9. * GNU General Public License for more details.
  10. *
  11. * You should have received a copy of the GNU General Public License
  12. * along with this program; if not, write to the Free Software
  13. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  14. *
  15. * Copyright (C) 2009 John Crispin <[email protected]>
  16. */
  17. #include <linux/module.h>
  18. #include <linux/kernel.h>
  19. #include <linux/types.h>
  20. #include <linux/dma-mapping.h>
  21. #include <linux/init.h>
  22. #include <linux/skbuff.h>
  23. #include <linux/etherdevice.h>
  24. #include <linux/ethtool.h>
  25. #include <linux/platform_device.h>
  26. #include <ramips_eth_platform.h>
  27. #include "ramips_eth.h"
  28. #define TX_TIMEOUT (20 * HZ / 100)
  29. #define MAX_RX_LENGTH 1600
  30. #ifdef CONFIG_RALINK_RT305X
  31. #include "ramips_esw.c"
  32. #endif
  33. #define phys_to_bus(a) (a & 0x1FFFFFFF)
  34. static struct net_device * ramips_dev;
  35. static void __iomem *ramips_fe_base = 0;
  36. static inline void
  37. ramips_fe_wr(u32 val, unsigned reg)
  38. {
  39. __raw_writel(val, ramips_fe_base + reg);
  40. }
  41. static inline u32
  42. ramips_fe_rr(unsigned reg)
  43. {
  44. return __raw_readl(ramips_fe_base + reg);
  45. }
  46. static inline void
  47. ramips_fe_int_disable(u32 mask)
  48. {
  49. ramips_fe_wr(ramips_fe_rr(RAMIPS_FE_INT_ENABLE) & ~mask,
  50. RAMIPS_FE_INT_ENABLE);
  51. /* flush write */
  52. ramips_fe_rr(RAMIPS_FE_INT_ENABLE);
  53. }
  54. static inline void
  55. ramips_fe_int_enable(u32 mask)
  56. {
  57. ramips_fe_wr(ramips_fe_rr(RAMIPS_FE_INT_ENABLE) | mask,
  58. RAMIPS_FE_INT_ENABLE);
  59. /* flush write */
  60. ramips_fe_rr(RAMIPS_FE_INT_ENABLE);
  61. }
  62. static inline void
  63. ramips_hw_set_macaddr(unsigned char *mac)
  64. {
  65. ramips_fe_wr((mac[0] << 8) | mac[1], RAMIPS_GDMA1_MAC_ADRH);
  66. ramips_fe_wr((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
  67. RAMIPS_GDMA1_MAC_ADRL);
  68. }
  69. #ifdef CONFIG_RALINK_RT288X
  70. static void
  71. ramips_setup_mdio_cfg(struct raeth_priv *re)
  72. {
  73. unsigned int mdio_cfg;
  74. mdio_cfg = RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 |
  75. RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 |
  76. RAMIPS_MDIO_CFG_GP1_FRC_EN;
  77. if (re->duplex == DUPLEX_FULL)
  78. mdio_cfg |= RAMIPS_MDIO_CFG_GP1_DUPLEX;
  79. if (re->tx_fc)
  80. mdio_cfg |= RAMIPS_MDIO_CFG_GP1_FC_TX;
  81. if (re->rx_fc)
  82. mdio_cfg |= RAMIPS_MDIO_CFG_GP1_FC_RX;
  83. switch (re->speed) {
  84. case SPEED_10:
  85. mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_10;
  86. break;
  87. case SPEED_100:
  88. mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_100;
  89. break;
  90. case SPEED_1000:
  91. mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_1000;
  92. break;
  93. default:
  94. BUG();
  95. }
  96. ramips_fe_wr(mdio_cfg, RAMIPS_MDIO_CFG);
  97. }
  98. #else
  99. static inline void ramips_setup_mdio_cfg(struct raeth_priv *re)
  100. {
  101. }
  102. #endif /* CONFIG_RALINK_RT288X */
  103. static void
  104. ramips_cleanup_dma(struct raeth_priv *re)
  105. {
  106. int i;
  107. for (i = 0; i < NUM_RX_DESC; i++)
  108. if (re->rx_skb[i])
  109. dev_kfree_skb_any(re->rx_skb[i]);
  110. if (re->rx)
  111. dma_free_coherent(NULL,
  112. NUM_RX_DESC * sizeof(struct ramips_rx_dma),
  113. re->rx, re->phy_rx);
  114. if (re->tx)
  115. dma_free_coherent(NULL,
  116. NUM_TX_DESC * sizeof(struct ramips_tx_dma),
  117. re->tx, re->phy_tx);
  118. }
  119. static int
  120. ramips_alloc_dma(struct raeth_priv *re)
  121. {
  122. int err = -ENOMEM;
  123. int i;
  124. re->skb_free_idx = 0;
  125. /* setup tx ring */
  126. re->tx = dma_alloc_coherent(NULL,
  127. NUM_TX_DESC * sizeof(struct ramips_tx_dma),
  128. &re->phy_tx, GFP_ATOMIC);
  129. if (!re->tx)
  130. goto err_cleanup;
  131. memset(re->tx, 0, NUM_TX_DESC * sizeof(struct ramips_tx_dma));
  132. for (i = 0; i < NUM_TX_DESC; i++) {
  133. re->tx[i].txd2 = TX_DMA_LSO | TX_DMA_DONE;
  134. re->tx[i].txd4 = TX_DMA_QN(3) | TX_DMA_PN(1);
  135. }
  136. /* setup rx ring */
  137. re->rx = dma_alloc_coherent(NULL,
  138. NUM_RX_DESC * sizeof(struct ramips_rx_dma),
  139. &re->phy_rx, GFP_ATOMIC);
  140. if (!re->rx)
  141. goto err_cleanup;
  142. memset(re->rx, 0, sizeof(struct ramips_rx_dma) * NUM_RX_DESC);
  143. for (i = 0; i < NUM_RX_DESC; i++) {
  144. struct sk_buff *new_skb = dev_alloc_skb(MAX_RX_LENGTH + 2);
  145. if (!new_skb)
  146. goto err_cleanup;
  147. skb_reserve(new_skb, 2);
  148. re->rx[i].rxd1 = dma_map_single(NULL,
  149. skb_put(new_skb, 2),
  150. MAX_RX_LENGTH + 2,
  151. DMA_FROM_DEVICE);
  152. re->rx[i].rxd2 |= RX_DMA_LSO;
  153. re->rx_skb[i] = new_skb;
  154. }
  155. return 0;
  156. err_cleanup:
  157. ramips_cleanup_dma(re);
  158. return err;
  159. }
  160. static void
  161. ramips_setup_dma(struct raeth_priv *re)
  162. {
  163. ramips_fe_wr(phys_to_bus(re->phy_tx), RAMIPS_TX_BASE_PTR0);
  164. ramips_fe_wr(NUM_TX_DESC, RAMIPS_TX_MAX_CNT0);
  165. ramips_fe_wr(0, RAMIPS_TX_CTX_IDX0);
  166. ramips_fe_wr(RAMIPS_PST_DTX_IDX0, RAMIPS_PDMA_RST_CFG);
  167. ramips_fe_wr(phys_to_bus(re->phy_rx), RAMIPS_RX_BASE_PTR0);
  168. ramips_fe_wr(NUM_RX_DESC, RAMIPS_RX_MAX_CNT0);
  169. ramips_fe_wr((NUM_RX_DESC - 1), RAMIPS_RX_CALC_IDX0);
  170. ramips_fe_wr(RAMIPS_PST_DRX_IDX0, RAMIPS_PDMA_RST_CFG);
  171. }
  172. static int
  173. ramips_eth_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
  174. {
  175. struct raeth_priv *priv = netdev_priv(dev);
  176. unsigned long tx;
  177. unsigned int tx_next;
  178. unsigned int mapped_addr;
  179. unsigned long flags;
  180. if (priv->plat->min_pkt_len) {
  181. if (skb->len < priv->plat->min_pkt_len) {
  182. if (skb_padto(skb, priv->plat->min_pkt_len)) {
  183. printk(KERN_ERR
  184. "ramips_eth: skb_padto failed\n");
  185. kfree_skb(skb);
  186. return 0;
  187. }
  188. skb_put(skb, priv->plat->min_pkt_len - skb->len);
  189. }
  190. }
  191. dev->trans_start = jiffies;
  192. mapped_addr = (unsigned int) dma_map_single(NULL, skb->data, skb->len,
  193. DMA_TO_DEVICE);
  194. dma_sync_single_for_device(NULL, mapped_addr, skb->len, DMA_TO_DEVICE);
  195. spin_lock_irqsave(&priv->page_lock, flags);
  196. tx = ramips_fe_rr(RAMIPS_TX_CTX_IDX0);
  197. tx_next = (tx + 1) % NUM_TX_DESC;
  198. if ((priv->tx_skb[tx]) || (priv->tx_skb[tx_next]) ||
  199. !(priv->tx[tx].txd2 & TX_DMA_DONE) ||
  200. !(priv->tx[tx_next].txd2 & TX_DMA_DONE))
  201. goto out;
  202. priv->tx[tx].txd1 = mapped_addr;
  203. priv->tx[tx].txd2 &= ~(TX_DMA_PLEN0_MASK | TX_DMA_DONE);
  204. priv->tx[tx].txd2 |= TX_DMA_PLEN0(skb->len);
  205. dev->stats.tx_packets++;
  206. dev->stats.tx_bytes += skb->len;
  207. priv->tx_skb[tx] = skb;
  208. wmb();
  209. ramips_fe_wr(tx_next, RAMIPS_TX_CTX_IDX0);
  210. spin_unlock_irqrestore(&priv->page_lock, flags);
  211. return NETDEV_TX_OK;
  212. out:
  213. spin_unlock_irqrestore(&priv->page_lock, flags);
  214. dev->stats.tx_dropped++;
  215. kfree_skb(skb);
  216. return NETDEV_TX_OK;
  217. }
  218. static void
  219. ramips_eth_rx_hw(unsigned long ptr)
  220. {
  221. struct net_device *dev = (struct net_device *) ptr;
  222. struct raeth_priv *priv = netdev_priv(dev);
  223. int rx;
  224. int max_rx = 16;
  225. while (max_rx) {
  226. struct sk_buff *rx_skb, *new_skb;
  227. rx = (ramips_fe_rr(RAMIPS_RX_CALC_IDX0) + 1) % NUM_RX_DESC;
  228. if (!(priv->rx[rx].rxd2 & RX_DMA_DONE))
  229. break;
  230. max_rx--;
  231. rx_skb = priv->rx_skb[rx];
  232. skb_put(rx_skb, RX_DMA_PLEN0(priv->rx[rx].rxd2));
  233. rx_skb->dev = dev;
  234. rx_skb->protocol = eth_type_trans(rx_skb, dev);
  235. rx_skb->ip_summed = CHECKSUM_NONE;
  236. dev->stats.rx_packets++;
  237. dev->stats.rx_bytes += rx_skb->len;
  238. netif_rx(rx_skb);
  239. new_skb = netdev_alloc_skb(dev, MAX_RX_LENGTH + 2);
  240. priv->rx_skb[rx] = new_skb;
  241. BUG_ON(!new_skb);
  242. skb_reserve(new_skb, 2);
  243. priv->rx[rx].rxd1 = dma_map_single(NULL,
  244. new_skb->data,
  245. MAX_RX_LENGTH + 2,
  246. DMA_FROM_DEVICE);
  247. priv->rx[rx].rxd2 &= ~RX_DMA_DONE;
  248. wmb();
  249. ramips_fe_wr(rx, RAMIPS_RX_CALC_IDX0);
  250. }
  251. if (max_rx == 0)
  252. tasklet_schedule(&priv->rx_tasklet);
  253. else
  254. ramips_fe_int_enable(RAMIPS_RX_DLY_INT);
  255. }
  256. static void
  257. ramips_eth_tx_housekeeping(unsigned long ptr)
  258. {
  259. struct net_device *dev = (struct net_device*)ptr;
  260. struct raeth_priv *priv = netdev_priv(dev);
  261. while ((priv->tx[priv->skb_free_idx].txd2 & TX_DMA_DONE) &&
  262. (priv->tx_skb[priv->skb_free_idx])) {
  263. dev_kfree_skb_irq(priv->tx_skb[priv->skb_free_idx]);
  264. priv->tx_skb[priv->skb_free_idx] = 0;
  265. priv->skb_free_idx++;
  266. if (priv->skb_free_idx >= NUM_TX_DESC)
  267. priv->skb_free_idx = 0;
  268. }
  269. ramips_fe_int_enable(RAMIPS_TX_DLY_INT);
  270. }
  271. static void
  272. ramips_eth_timeout(struct net_device *dev)
  273. {
  274. struct raeth_priv *priv = netdev_priv(dev);
  275. tasklet_schedule(&priv->tx_housekeeping_tasklet);
  276. }
  277. static irqreturn_t
  278. ramips_eth_irq(int irq, void *dev)
  279. {
  280. struct raeth_priv *priv = netdev_priv(dev);
  281. unsigned long fe_int = ramips_fe_rr(RAMIPS_FE_INT_STATUS);
  282. ramips_fe_wr(0xFFFFFFFF, RAMIPS_FE_INT_STATUS);
  283. if (fe_int & RAMIPS_RX_DLY_INT) {
  284. ramips_fe_int_disable(RAMIPS_RX_DLY_INT);
  285. tasklet_schedule(&priv->rx_tasklet);
  286. }
  287. if (fe_int & RAMIPS_TX_DLY_INT)
  288. ramips_eth_tx_housekeeping((unsigned long)dev);
  289. return IRQ_HANDLED;
  290. }
  291. static int
  292. ramips_eth_open(struct net_device *dev)
  293. {
  294. struct raeth_priv *priv = netdev_priv(dev);
  295. int err;
  296. err = request_irq(dev->irq, ramips_eth_irq, IRQF_DISABLED,
  297. dev->name, dev);
  298. if (err)
  299. return err;
  300. err = ramips_alloc_dma(priv);
  301. if (err)
  302. goto err_free_irq;
  303. ramips_hw_set_macaddr(dev->dev_addr);
  304. ramips_setup_dma(priv);
  305. ramips_fe_wr((ramips_fe_rr(RAMIPS_PDMA_GLO_CFG) & 0xff) |
  306. (RAMIPS_TX_WB_DDONE | RAMIPS_RX_DMA_EN |
  307. RAMIPS_TX_DMA_EN | RAMIPS_PDMA_SIZE_4DWORDS),
  308. RAMIPS_PDMA_GLO_CFG);
  309. ramips_fe_wr((ramips_fe_rr(RAMIPS_FE_GLO_CFG) &
  310. ~(RAMIPS_US_CYC_CNT_MASK << RAMIPS_US_CYC_CNT_SHIFT)) |
  311. ((priv->plat->sys_freq / RAMIPS_US_CYC_CNT_DIVISOR) << RAMIPS_US_CYC_CNT_SHIFT),
  312. RAMIPS_FE_GLO_CFG);
  313. tasklet_init(&priv->tx_housekeeping_tasklet, ramips_eth_tx_housekeeping,
  314. (unsigned long)dev);
  315. tasklet_init(&priv->rx_tasklet, ramips_eth_rx_hw, (unsigned long)dev);
  316. ramips_setup_mdio_cfg(priv);
  317. ramips_fe_wr(RAMIPS_DELAY_INIT, RAMIPS_DLY_INT_CFG);
  318. ramips_fe_wr(RAMIPS_TX_DLY_INT | RAMIPS_RX_DLY_INT, RAMIPS_FE_INT_ENABLE);
  319. ramips_fe_wr(ramips_fe_rr(RAMIPS_GDMA1_FWD_CFG) &
  320. ~(RAMIPS_GDM1_ICS_EN | RAMIPS_GDM1_TCS_EN | RAMIPS_GDM1_UCS_EN | 0xffff),
  321. RAMIPS_GDMA1_FWD_CFG);
  322. ramips_fe_wr(ramips_fe_rr(RAMIPS_CDMA_CSG_CFG) &
  323. ~(RAMIPS_ICS_GEN_EN | RAMIPS_TCS_GEN_EN | RAMIPS_UCS_GEN_EN),
  324. RAMIPS_CDMA_CSG_CFG);
  325. ramips_fe_wr(RAMIPS_PSE_FQFC_CFG_INIT, RAMIPS_PSE_FQ_CFG);
  326. ramips_fe_wr(1, RAMIPS_FE_RST_GL);
  327. ramips_fe_wr(0, RAMIPS_FE_RST_GL);
  328. netif_start_queue(dev);
  329. return 0;
  330. err_free_irq:
  331. free_irq(dev->irq, dev);
  332. return err;
  333. }
  334. static int
  335. ramips_eth_stop(struct net_device *dev)
  336. {
  337. struct raeth_priv *priv = netdev_priv(dev);
  338. ramips_fe_wr(ramips_fe_rr(RAMIPS_PDMA_GLO_CFG) &
  339. ~(RAMIPS_TX_WB_DDONE | RAMIPS_RX_DMA_EN | RAMIPS_TX_DMA_EN),
  340. RAMIPS_PDMA_GLO_CFG);
  341. /* disable all interrupts in the hw */
  342. ramips_fe_wr(0, RAMIPS_FE_INT_ENABLE);
  343. free_irq(dev->irq, dev);
  344. netif_stop_queue(dev);
  345. tasklet_kill(&priv->tx_housekeeping_tasklet);
  346. tasklet_kill(&priv->rx_tasklet);
  347. ramips_cleanup_dma(priv);
  348. printk(KERN_DEBUG "ramips_eth: stopped\n");
  349. return 0;
  350. }
  351. static int __init
  352. ramips_eth_probe(struct net_device *dev)
  353. {
  354. struct raeth_priv *priv = netdev_priv(dev);
  355. BUG_ON(!priv->plat->reset_fe);
  356. priv->plat->reset_fe();
  357. net_srandom(jiffies);
  358. memcpy(dev->dev_addr, priv->plat->mac, ETH_ALEN);
  359. ether_setup(dev);
  360. dev->mtu = 1500;
  361. dev->watchdog_timeo = TX_TIMEOUT;
  362. spin_lock_init(&priv->page_lock);
  363. return 0;
  364. }
  365. static const struct net_device_ops ramips_eth_netdev_ops = {
  366. .ndo_init = ramips_eth_probe,
  367. .ndo_open = ramips_eth_open,
  368. .ndo_stop = ramips_eth_stop,
  369. .ndo_start_xmit = ramips_eth_hard_start_xmit,
  370. .ndo_tx_timeout = ramips_eth_timeout,
  371. .ndo_change_mtu = eth_change_mtu,
  372. .ndo_set_mac_address = eth_mac_addr,
  373. .ndo_validate_addr = eth_validate_addr,
  374. };
  375. static int
  376. ramips_eth_plat_probe(struct platform_device *plat)
  377. {
  378. struct raeth_priv *priv;
  379. struct ramips_eth_platform_data *data = plat->dev.platform_data;
  380. struct resource *res;
  381. int err;
  382. if (!data) {
  383. dev_err(&plat->dev, "no platform data specified\n");
  384. return -EINVAL;
  385. }
  386. res = platform_get_resource(plat, IORESOURCE_MEM, 0);
  387. if (!res) {
  388. dev_err(&plat->dev, "no memory resource found\n");
  389. return -ENXIO;
  390. }
  391. ramips_fe_base = ioremap_nocache(res->start, res->end - res->start + 1);
  392. if (!ramips_fe_base)
  393. return -ENOMEM;
  394. ramips_dev = alloc_etherdev(sizeof(struct raeth_priv));
  395. if (!ramips_dev) {
  396. dev_err(&plat->dev, "alloc_etherdev failed\n");
  397. err = -ENOMEM;
  398. goto err_unmap;
  399. }
  400. strcpy(ramips_dev->name, "eth%d");
  401. ramips_dev->irq = platform_get_irq(plat, 0);
  402. if (ramips_dev->irq < 0) {
  403. dev_err(&plat->dev, "no IRQ resource found\n");
  404. err = -ENXIO;
  405. goto err_free_dev;
  406. }
  407. ramips_dev->addr_len = ETH_ALEN;
  408. ramips_dev->base_addr = (unsigned long)ramips_fe_base;
  409. ramips_dev->netdev_ops = &ramips_eth_netdev_ops;
  410. priv = netdev_priv(ramips_dev);
  411. priv->speed = data->speed;
  412. priv->duplex = data->duplex;
  413. priv->rx_fc = data->rx_fc;
  414. priv->tx_fc = data->tx_fc;
  415. priv->plat = data;
  416. err = register_netdev(ramips_dev);
  417. if (err) {
  418. dev_err(&plat->dev, "error bringing up device\n");
  419. goto err_free_dev;
  420. }
  421. #ifdef CONFIG_RALINK_RT305X
  422. rt305x_esw_init();
  423. #endif
  424. printk(KERN_DEBUG "ramips_eth: loaded\n");
  425. return 0;
  426. err_free_dev:
  427. kfree(ramips_dev);
  428. err_unmap:
  429. iounmap(ramips_fe_base);
  430. return err;
  431. }
  432. static int
  433. ramips_eth_plat_remove(struct platform_device *plat)
  434. {
  435. unregister_netdev(ramips_dev);
  436. free_netdev(ramips_dev);
  437. printk(KERN_DEBUG "ramips_eth: unloaded\n");
  438. return 0;
  439. }
  440. static struct platform_driver ramips_eth_driver = {
  441. .probe = ramips_eth_plat_probe,
  442. .remove = ramips_eth_plat_remove,
  443. .driver = {
  444. .name = "ramips_eth",
  445. .owner = THIS_MODULE,
  446. },
  447. };
  448. static int __init
  449. ramips_eth_init(void)
  450. {
  451. int ret = platform_driver_register(&ramips_eth_driver);
  452. if (ret)
  453. printk(KERN_ERR
  454. "ramips_eth: Error registering platfom driver!\n");
  455. return ret;
  456. }
  457. static void __exit
  458. ramips_eth_cleanup(void)
  459. {
  460. platform_driver_unregister(&ramips_eth_driver);
  461. }
  462. module_init(ramips_eth_init);
  463. module_exit(ramips_eth_cleanup);
  464. MODULE_LICENSE("GPL");
  465. MODULE_AUTHOR("John Crispin <[email protected]>");
  466. MODULE_DESCRIPTION("ethernet driver for ramips boards");