qcom-ipq4019-mf18a.dts 8.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. // Copyright (c) 2022, Pawel Dembicki <[email protected]>.
  3. // Copyright (c) 2022, Marcin Gajda <[email protected]>.
  4. #include "qcom-ipq4019.dtsi"
  5. #include <dt-bindings/soc/qcom,tcsr.h>
  6. #include <dt-bindings/gpio/gpio.h>
  7. #include <dt-bindings/input/input.h>
  8. #include <dt-bindings/leds/common.h>
  9. / {
  10. model = "ZTE MF18A";
  11. compatible = "zte,mf18a";
  12. aliases {
  13. led-boot = &led_power;
  14. led-failsafe = &led_power;
  15. led-running = &led_power;
  16. led-upgrade = &led_power;
  17. };
  18. chosen {
  19. /*
  20. * bootargs forced by u-boot bootipq command:
  21. * 'ubi.mtd=rootfs root=mtd:ubi_rootfs rootfstype=squashfs rootwait'
  22. */
  23. bootargs-append = " root=/dev/ubiblock0_1";
  24. };
  25. gpio-restart {
  26. compatible = "gpio-restart";
  27. gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
  28. };
  29. leds {
  30. compatible = "gpio-leds";
  31. led_internal: led-0 {
  32. label = "blue:internal";
  33. gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
  34. default-state = "keep";
  35. };
  36. led_power: led-1 {
  37. label = "blue:power";
  38. gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
  39. default-state = "keep";
  40. };
  41. led-2 {
  42. function = LED_FUNCTION_WLAN;
  43. label = "blue:wlan";
  44. gpios = <&tlmm 23 GPIO_ACTIVE_HIGH>;
  45. linux,default-trigger = "phy0tpt";
  46. };
  47. led-3 {
  48. label = "red:wlan";
  49. gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
  50. };
  51. led-4 {
  52. function = LED_FUNCTION_WLAN;
  53. label = "blue:smart";
  54. gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
  55. linux,default-trigger = "phy1tpt";
  56. };
  57. led-5 {
  58. label = "red:smart";
  59. gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
  60. };
  61. resetzwave {
  62. label = "resetzwave";
  63. gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
  64. };
  65. };
  66. keys {
  67. compatible = "gpio-keys";
  68. reset {
  69. label = "reset";
  70. linux,code = <KEY_RESTART>;
  71. gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
  72. };
  73. wps {
  74. label = "wps";
  75. linux,code = <KEY_WPS_BUTTON>;
  76. gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
  77. };
  78. };
  79. soc {
  80. rng@22000 {
  81. status = "okay";
  82. };
  83. mdio@90000 {
  84. status = "okay";
  85. pinctrl-0 = <&mdio_pins>;
  86. pinctrl-names = "default";
  87. reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
  88. reset-delay-us = <2000>;
  89. };
  90. tcsr@1949000 {
  91. compatible = "qcom,tcsr";
  92. reg = <0x1949000 0x100>;
  93. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  94. };
  95. tcsr@194b000 {
  96. /* select hostmode */
  97. compatible = "qcom,tcsr";
  98. reg = <0x194b000 0x100>;
  99. qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  100. status = "okay";
  101. };
  102. ess_tcsr@1953000 {
  103. compatible = "qcom,tcsr";
  104. reg = <0x1953000 0x1000>;
  105. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  106. };
  107. tcsr@1957000 {
  108. compatible = "qcom,tcsr";
  109. reg = <0x1957000 0x100>;
  110. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  111. };
  112. usb2@60f8800 {
  113. status = "okay";
  114. };
  115. usb3@8af8800 {
  116. status = "okay";
  117. };
  118. crypto@8e3a000 {
  119. status = "okay";
  120. };
  121. watchdog@b017000 {
  122. status = "okay";
  123. };
  124. };
  125. };
  126. &blsp_dma {
  127. status = "okay";
  128. };
  129. &blsp1_spi1 {
  130. pinctrl-0 = <&spi_0_pins>;
  131. pinctrl-names = "default";
  132. status = "okay";
  133. cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
  134. flash@0 {
  135. /* u-boot is looking for "n25q128a11" property */
  136. compatible = "jedec,spi-nor", "n25q128a11";
  137. #address-cells = <1>;
  138. #size-cells = <1>;
  139. reg = <0>;
  140. spi-max-frequency = <24000000>;
  141. partitions {
  142. compatible = "fixed-partitions";
  143. #address-cells = <1>;
  144. #size-cells = <1>;
  145. partition@0 {
  146. label = "0:SBL1";
  147. reg = <0x0 0x40000>;
  148. read-only;
  149. };
  150. partition@40000 {
  151. label = "0:MIBIB";
  152. reg = <0x40000 0x20000>;
  153. read-only;
  154. };
  155. partition@60000 {
  156. label = "0:QSEE";
  157. reg = <0x60000 0x60000>;
  158. read-only;
  159. };
  160. partition@c0000 {
  161. label = "0:CDT";
  162. reg = <0xc0000 0x10000>;
  163. read-only;
  164. };
  165. partition@d0000 {
  166. label = "0:DDRPARAMS";
  167. reg = <0xd0000 0x10000>;
  168. read-only;
  169. };
  170. partition@e0000 {
  171. label = "0:APPSBLENV";
  172. reg = <0xe0000 0x10000>;
  173. read-only;
  174. };
  175. partition@f0000 {
  176. label = "0:APPSBL";
  177. reg = <0xf0000 0xc0000>;
  178. read-only;
  179. };
  180. partition@1b0000 {
  181. label = "0:reserved1";
  182. reg = <0x1b0000 0x50000>;
  183. read-only;
  184. };
  185. };
  186. };
  187. };
  188. &blsp1_uart1 {
  189. pinctrl-0 = <&serial_pins>;
  190. pinctrl-names = "default";
  191. status = "okay";
  192. };
  193. &cryptobam {
  194. status = "okay";
  195. };
  196. &gmac {
  197. status = "okay";
  198. nvmem-cell-names = "mac-address";
  199. nvmem-cells = <&macaddr_config_0 0>;
  200. };
  201. &switch {
  202. status = "okay";
  203. };
  204. &swport2 {
  205. status = "okay";
  206. label = "wan";
  207. nvmem-cell-names = "mac-address";
  208. nvmem-cells = <&macaddr_config_0 1>;
  209. };
  210. &swport3 {
  211. status = "okay";
  212. label = "lan";
  213. };
  214. &nand {
  215. pinctrl-0 = <&nand_pins>;
  216. pinctrl-names = "default";
  217. status = "okay";
  218. nand@0 {
  219. partitions {
  220. compatible = "fixed-partitions";
  221. #address-cells = <1>;
  222. #size-cells = <1>;
  223. partition@0 {
  224. label = "fota-flag";
  225. reg = <0x0 0xa0000>;
  226. read-only;
  227. };
  228. partition@a0000 {
  229. label = "ART";
  230. reg = <0xa0000 0x80000>;
  231. read-only;
  232. nvmem-layout {
  233. compatible = "fixed-layout";
  234. #address-cells = <1>;
  235. #size-cells = <1>;
  236. precal_art_1000: precal@1000 {
  237. reg = <0x1000 0x2f20>;
  238. };
  239. precal_art_9000: precal@9000 {
  240. reg = <0x9000 0x2f20>;
  241. };
  242. };
  243. };
  244. partition@120000 {
  245. label = "mac";
  246. reg = <0x120000 0x80000>;
  247. read-only;
  248. nvmem-layout {
  249. compatible = "fixed-layout";
  250. #address-cells = <1>;
  251. #size-cells = <1>;
  252. macaddr_config_0: macaddr@0 {
  253. compatible = "mac-base";
  254. reg = <0x0 0x6>;
  255. #nvmem-cell-cells = <1>;
  256. };
  257. };
  258. };
  259. partition@1a0000 {
  260. label = "reserved2";
  261. reg = <0x1a0000 0xc0000>;
  262. read-only;
  263. };
  264. partition@260000 {
  265. label = "cfg-param";
  266. reg = <0x260000 0x400000>;
  267. read-only;
  268. };
  269. partition@660000 {
  270. label = "log";
  271. reg = <0x660000 0x400000>;
  272. };
  273. partition@a60000 {
  274. label = "oops";
  275. reg = <0xa60000 0xa0000>;
  276. };
  277. partition@b00000 {
  278. label = "reserved3";
  279. reg = <0xb00000 0x500000>;
  280. read-only;
  281. };
  282. partition@1000000 {
  283. label = "web";
  284. reg = <0x1000000 0x800000>;
  285. };
  286. partition@1800000 {
  287. label = "rootfs";
  288. reg = <0x1800000 0x1d00000>;
  289. };
  290. partition@3500000 {
  291. label = "data";
  292. reg = <0x3500000 0x1900000>;
  293. };
  294. partition@4e00000 {
  295. label = "fota";
  296. reg = <0x4e00000 0x2800000>;
  297. };
  298. partition@7600000 {
  299. label = "iot-db";
  300. reg = <0x7600000 0xa00000>;
  301. };
  302. };
  303. };
  304. };
  305. &qpic_bam {
  306. status = "okay";
  307. };
  308. &tlmm {
  309. i2c_0_pins: i2c_0_pinmux {
  310. mux {
  311. pins = "gpio20", "gpio21";
  312. function = "blsp_i2c0";
  313. bias-disable;
  314. };
  315. };
  316. mdio_pins: mdio_pinmux {
  317. mux_1 {
  318. pins = "gpio6";
  319. function = "mdio";
  320. bias-pull-up;
  321. };
  322. mux_2 {
  323. pins = "gpio7";
  324. function = "mdc";
  325. bias-pull-up;
  326. };
  327. };
  328. nand_pins: nand_pins {
  329. pullups {
  330. pins = "gpio52", "gpio53", "gpio58",
  331. "gpio59";
  332. function = "qpic";
  333. bias-pull-up;
  334. };
  335. pulldowns {
  336. pins = "gpio54", "gpio55", "gpio56",
  337. "gpio57", "gpio60",
  338. "gpio62", "gpio63", "gpio64",
  339. "gpio65", "gpio66", "gpio67",
  340. "gpio69";
  341. function = "qpic";
  342. bias-pull-down;
  343. };
  344. };
  345. serial_pins: serial_pinmux {
  346. mux {
  347. pins = "gpio16", "gpio17";
  348. function = "blsp_uart0";
  349. bias-disable;
  350. };
  351. };
  352. spi_0_pins: spi_0_pinmux {
  353. pinmux {
  354. function = "blsp_spi0";
  355. pins = "gpio13", "gpio14", "gpio15";
  356. drive-strength = <12>;
  357. bias-disable;
  358. };
  359. pinmux_cs {
  360. function = "gpio";
  361. pins = "gpio12";
  362. drive-strength = <2>;
  363. bias-disable;
  364. output-high;
  365. };
  366. };
  367. };
  368. &usb2_hs_phy {
  369. status = "okay";
  370. };
  371. &usb3_ss_phy {
  372. status = "okay";
  373. };
  374. &usb3_hs_phy {
  375. status = "okay";
  376. };
  377. &wifi0 {
  378. status = "okay";
  379. nvmem-cell-names = "pre-calibration", "mac-address";
  380. nvmem-cells = <&precal_art_1000>, <&macaddr_config_0 2>;
  381. qcom,ath10k-calibration-variant = "ZTE-MF18A";
  382. };
  383. //* This node is used for 5Ghz on QCA9982 */
  384. &pcie0 {
  385. status = "okay";
  386. perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
  387. wake-gpio = <&tlmm 40 GPIO_ACTIVE_LOW>;
  388. clkreq-gpio = <&tlmm 39 GPIO_ACTIVE_LOW>;
  389. bridge@0,0 {
  390. reg = <0x00000000 0 0 0 0>;
  391. #address-cells = <3>;
  392. #size-cells = <2>;
  393. ranges;
  394. wifi2: wifi@1,0 {
  395. compatible = "pci168c,0040";
  396. nvmem-cell-names = "pre-calibration", "mac-address";
  397. nvmem-cells = <&precal_art_9000>, <&macaddr_config_0 3>;
  398. qcom,ath10k-calibration-variant = "ZTE-MF18A";
  399. reg = <0x00010000 0 0 0 0>;
  400. };
  401. };
  402. };