qcom-ipq4019-whw03v2.dts 8.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "qcom-ipq4019.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. #include <dt-bindings/soc/qcom,tcsr.h>
  6. #include <dt-bindings/leds/common.h>
  7. / {
  8. model = "Linksys WHW03 V2 (Velop)";
  9. compatible = "linksys,whw03v2", "qcom,ipq4019";
  10. aliases {
  11. led-boot = &led_blue;
  12. led-failsafe = &led_red;
  13. led-running = &led_green;
  14. led-upgrade = &led_red;
  15. };
  16. // The arguments rootfstype and ro are needed
  17. // to override the default bootargs
  18. chosen {
  19. bootargs-append = " root=/dev/ubiblock0_0 rootfstype=squashfs ro";
  20. stdout-path = &blsp1_uart1;
  21. };
  22. soc {
  23. ess-tcsr@1953000 {
  24. compatible = "qcom,tcsr";
  25. reg = <0x1953000 0x1000>;
  26. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  27. };
  28. tcsr@1949000 {
  29. compatible = "qcom,tcsr";
  30. reg = <0x1949000 0x100>;
  31. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  32. };
  33. tcsr@194b000 {
  34. compatible = "qcom,tcsr";
  35. reg = <0x194b000 0x100>;
  36. qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  37. };
  38. tcsr@1957000 {
  39. compatible = "qcom,tcsr";
  40. reg = <0x1957000 0x100>;
  41. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  42. };
  43. };
  44. keys {
  45. compatible = "gpio-keys";
  46. reset {
  47. label = "reset";
  48. gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
  49. linux,code = <KEY_RESTART>;
  50. };
  51. };
  52. };
  53. &tlmm {
  54. mdio_pins: mdio-pinmux {
  55. mux-1 {
  56. pins = "gpio6";
  57. function = "mdio";
  58. bias-pull-up;
  59. };
  60. mux-2 {
  61. pins = "gpio7";
  62. function = "mdc";
  63. bias-pull-up;
  64. };
  65. };
  66. i2c_0_pins: i2c-0-pinmux {
  67. mux {
  68. function = "blsp_i2c0";
  69. pins = "gpio20", "gpio21";
  70. bias-disable;
  71. };
  72. };
  73. serial_0_pins: serial0-pinmux {
  74. mux {
  75. pins = "gpio16", "gpio17";
  76. function = "blsp_uart0";
  77. bias-disable;
  78. };
  79. };
  80. serial_1_pins: serial1-pinmux {
  81. mux {
  82. pins = "gpio8", "gpio9", "gpio10", "gpio11";
  83. function = "blsp_uart1";
  84. bias-disable;
  85. };
  86. };
  87. spi_0_pins: spi-0-pinmux {
  88. mux {
  89. function = "blsp_spi0";
  90. pins = "gpio13", "gpio14", "gpio15";
  91. drive-strength = <12>;
  92. bias-disable;
  93. };
  94. mux-cs {
  95. pins = "gpio12";
  96. drive-strength = <2>;
  97. bias-disable;
  98. output-high;
  99. };
  100. };
  101. spi_1_pins: spi-1-pinmux {
  102. mux-1 {
  103. function = "blsp_spi1";
  104. pins = "gpio44", "gpio46","gpio47";
  105. bias-disable;
  106. };
  107. mux-2 {
  108. pins = "gpio31", "gpio45", "gpio49";
  109. function = "gpio";
  110. bias-pull-up;
  111. output-high;
  112. };
  113. host-interrupt {
  114. pins = "gpio42";
  115. function = "gpio";
  116. input;
  117. };
  118. };
  119. wifi_0_pins: wifi0-pinmux {
  120. btcoexist {
  121. bias-pull-up;
  122. drive-strength = <6>;
  123. function = "gpio";
  124. output-high;
  125. pins = "gpio52";
  126. };
  127. };
  128. zigbee-0 {
  129. gpio-hog;
  130. gpios = <29 GPIO_ACTIVE_HIGH>;
  131. bias-disable;
  132. output-low;
  133. };
  134. zigbee-1 {
  135. gpio-hog;
  136. gpios = <50 GPIO_ACTIVE_HIGH>;
  137. bias-disable;
  138. input;
  139. };
  140. bluetooth-enable {
  141. gpio-hog;
  142. gpios = <32 GPIO_ACTIVE_HIGH>;
  143. output-high;
  144. };
  145. };
  146. &mdio {
  147. status = "okay";
  148. pinctrl-0 = <&mdio_pins>;
  149. pinctrl-names = "default";
  150. phy-reset-gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;
  151. };
  152. &ethphy0 {
  153. status = "disabled";
  154. };
  155. &ethphy1 {
  156. status = "disabled";
  157. };
  158. &ethphy2 {
  159. status = "disabled";
  160. };
  161. &ethphy3 {
  162. reg = <0x1b>;
  163. };
  164. &ethphy4 {
  165. reg = <0x1c>;
  166. };
  167. &psgmiiphy {
  168. reg = <0x1d>;
  169. };
  170. &watchdog {
  171. status = "okay";
  172. };
  173. &prng {
  174. status = "okay";
  175. };
  176. &blsp_dma {
  177. status = "okay";
  178. };
  179. &cryptobam {
  180. num-channels = <4>;
  181. qcom,num-ees = <2>;
  182. status = "okay";
  183. };
  184. &crypto {
  185. status = "okay";
  186. };
  187. &blsp1_uart1 {
  188. status = "okay";
  189. pinctrl-0 = <&serial_0_pins>;
  190. pinctrl-names = "default";
  191. };
  192. &blsp1_uart2 {
  193. status = "okay";
  194. pinctrl-0 = <&serial_1_pins>;
  195. pinctrl-names = "default";
  196. bluetooth {
  197. compatible = "csr,8811";
  198. enable-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
  199. };
  200. };
  201. &blsp1_spi2 {
  202. pinctrl-0 = <&spi_1_pins>;
  203. pinctrl-names = "default";
  204. status = "okay";
  205. cs-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
  206. zigbee@0 {
  207. #address-cells = <1>;
  208. #size-cells = <0>;
  209. compatible = "silabs,em3581";
  210. reg = <0>;
  211. spi-max-frequency = <12000000>;
  212. };
  213. };
  214. &blsp1_i2c3 {
  215. pinctrl-0 = <&i2c_0_pins>;
  216. pinctrl-names = "default";
  217. status = "okay";
  218. // RGB LEDs
  219. pca9633: led-controller@62 {
  220. compatible = "nxp,pca9633";
  221. nxp,hw-blink;
  222. reg = <0x62>;
  223. #address-cells = <1>;
  224. #size-cells = <0>;
  225. led_red: red@0 {
  226. label = "red";
  227. color = <LED_COLOR_ID_RED>;
  228. function = LED_FUNCTION_INDICATOR;
  229. linux,default-trigger = "none";
  230. reg = <0>;
  231. };
  232. led_green: green@1 {
  233. label = "green";
  234. color = <LED_COLOR_ID_GREEN>;
  235. function = LED_FUNCTION_INDICATOR;
  236. linux,default-trigger = "none";
  237. reg = <1>;
  238. };
  239. led_blue: blue@2 {
  240. label = "blue";
  241. color = <LED_COLOR_ID_BLUE>;
  242. function = LED_FUNCTION_INDICATOR;
  243. linux,default-trigger = "default-on";
  244. reg = <2>;
  245. };
  246. };
  247. };
  248. &usb3_ss_phy {
  249. status = "okay";
  250. };
  251. &usb3_hs_phy {
  252. status = "okay";
  253. };
  254. &usb2_hs_phy {
  255. status = "okay";
  256. };
  257. &nand {
  258. status = "okay";
  259. nand@0 {
  260. partitions {
  261. compatible = "fixed-partitions";
  262. #address-cells = <1>;
  263. #size-cells = <1>;
  264. partition@0 {
  265. label = "SBL1";
  266. reg = <0x0 0x100000>;
  267. read-only;
  268. };
  269. partition@100000 {
  270. label = "MIBIB";
  271. reg = <0x100000 0x100000>;
  272. read-only;
  273. };
  274. partition@200000 {
  275. label = "QSEE";
  276. reg = <0x200000 0x100000>;
  277. read-only;
  278. };
  279. partition@300000 {
  280. label = "CDT";
  281. reg = <0x300000 0x80000>;
  282. read-only;
  283. };
  284. partition@380000 {
  285. label = "APPSBL";
  286. reg = <0x380000 0x200000>;
  287. read-only;
  288. };
  289. partition@580000 {
  290. label = "ART";
  291. reg = <0x580000 0x80000>;
  292. read-only;
  293. nvmem-layout {
  294. compatible = "fixed-layout";
  295. #address-cells = <1>;
  296. #size-cells = <1>;
  297. macaddr_gmac0: macaddr@0 {
  298. compatible = "mac-base";
  299. reg = <0x0 0x6>;
  300. #nvmem-cell-cells = <1>;
  301. };
  302. macaddr_gmac1: macaddr@6 {
  303. reg = <0x6 0x6>;
  304. };
  305. precal_art_1000: precal@1000 {
  306. reg = <0x1000 0x2f20>;
  307. };
  308. precal_art_5000: precal@5000 {
  309. reg = <0x5000 0x2f20>;
  310. };
  311. precal_art_9000: precal@9000 {
  312. reg = <0x9000 0x2f20>;
  313. };
  314. };
  315. };
  316. partition@600000 {
  317. label = "u_env";
  318. reg = <0x600000 0x80000>;
  319. };
  320. partition@680000 {
  321. label = "s_env";
  322. reg = <0x680000 0x40000>;
  323. };
  324. partition@6c0000 {
  325. label = "devinfo";
  326. reg = <0x6c0000 0x40000>;
  327. read-only;
  328. };
  329. partition@700000 {
  330. label = "kernel";
  331. reg = <0x700000 0xa100000>;
  332. };
  333. partition@d00000 {
  334. label = "rootfs";
  335. reg = <0xd00000 0x9b00000>;
  336. };
  337. partition@a800000 {
  338. label = "alt_kernel";
  339. reg = <0xa800000 0xa100000>;
  340. };
  341. partition@ae00000 {
  342. label = "alt_rootfs";
  343. reg = <0xae00000 0x9b00000>;
  344. };
  345. partition@14900000 {
  346. label = "sysdiag";
  347. reg = <0x14900000 0x200000>;
  348. read-only;
  349. };
  350. partition@14b00000 {
  351. label = "syscfg";
  352. reg = <0x14b00000 0xb500000>;
  353. read-only;
  354. };
  355. };
  356. };
  357. };
  358. &pcie0 {
  359. status = "okay";
  360. perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
  361. wake-gpios = <&tlmm 40 GPIO_ACTIVE_LOW>;
  362. clkreq-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
  363. bridge@0,0 {
  364. reg = <0x00000000 0 0 0 0>;
  365. #address-cells = <3>;
  366. #size-cells = <2>;
  367. ranges;
  368. wifi2: wifi@1,0 {
  369. compatible = "qcom,ath10k";
  370. reg = <0x00010000 0 0 0 0>;
  371. };
  372. };
  373. };
  374. &qpic_bam {
  375. status = "okay";
  376. };
  377. &gmac {
  378. status = "okay";
  379. };
  380. &switch {
  381. status = "okay";
  382. };
  383. &swport4 {
  384. status = "okay";
  385. label = "lan";
  386. nvmem-cell-names = "mac-address";
  387. nvmem-cells = <&macaddr_gmac1>;
  388. };
  389. &swport5 {
  390. status = "okay";
  391. label = "wan";
  392. nvmem-cell-names = "mac-address";
  393. nvmem-cells = <&macaddr_gmac0 0>;
  394. };
  395. &wifi0 {
  396. pinctrl-0 = <&wifi_0_pins>;
  397. pinctrl-names = "default";
  398. status = "okay";
  399. qcom,coexist-support = <1>;
  400. qcom,coexist-gpio-pin = <0x34>;
  401. ieee80211-freq-limit = <2401000 2473000>;
  402. qcom,ath10k-calibration-variant = "linksys-whw03v2";
  403. nvmem-cell-names = "pre-calibration", "mac-address";
  404. nvmem-cells = <&precal_art_1000>, <&macaddr_gmac0 1>;
  405. };
  406. &wifi1 {
  407. status = "okay";
  408. ieee80211-freq-limit = <5170000 5250000>;
  409. qcom,ath10k-calibration-variant = "linksys-whw03v2";
  410. nvmem-cell-names = "pre-calibration", "mac-address";
  411. nvmem-cells = <&precal_art_5000>, <&macaddr_gmac0 2>;
  412. };
  413. &wifi2 {
  414. status = "okay";
  415. ieee80211-freq-limit = <5735000 5835000>;
  416. qcom,ath10k-calibration-variant = "linksys-whw03v2";
  417. nvmem-cell-names = "pre-calibration", "mac-address";
  418. nvmem-cells = <&precal_art_9000>, <&macaddr_gmac0 3>;
  419. };