qcom-ipq4019-cm520-79f.dts 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "qcom-ipq4019.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. #include <dt-bindings/soc/qcom,tcsr.h>
  6. / {
  7. model = "MobiPromo CM520-79F";
  8. compatible = "mobipromo,cm520-79f";
  9. aliases {
  10. led-boot = &led_sys;
  11. led-failsafe = &led_sys;
  12. led-running = &led_sys;
  13. led-upgrade = &led_sys;
  14. };
  15. soc {
  16. rng@22000 {
  17. status = "okay";
  18. };
  19. mdio@90000 {
  20. status = "okay";
  21. pinctrl-0 = <&mdio_pins>;
  22. pinctrl-names = "default";
  23. reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
  24. reset-delay-us = <1000>;
  25. };
  26. ess-psgmii@98000 {
  27. status = "okay";
  28. };
  29. tcsr@1949000 {
  30. compatible = "qcom,tcsr";
  31. reg = <0x1949000 0x100>;
  32. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  33. };
  34. tcsr@194b000 {
  35. compatible = "qcom,tcsr";
  36. reg = <0x194b000 0x100>;
  37. qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  38. };
  39. ess_tcsr@1953000 {
  40. compatible = "qcom,tcsr";
  41. reg = <0x1953000 0x1000>;
  42. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  43. };
  44. tcsr@1957000 {
  45. compatible = "qcom,tcsr";
  46. reg = <0x1957000 0x100>;
  47. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  48. };
  49. usb2@60f8800 {
  50. status = "okay";
  51. dwc3@6000000 {
  52. #address-cells = <1>;
  53. #size-cells = <0>;
  54. usb2_port1: port@1 {
  55. reg = <1>;
  56. #trigger-source-cells = <0>;
  57. };
  58. };
  59. };
  60. usb3@8af8800 {
  61. status = "okay";
  62. dwc3@8a00000 {
  63. #address-cells = <1>;
  64. #size-cells = <0>;
  65. usb3_port1: port@1 {
  66. reg = <1>;
  67. #trigger-source-cells = <0>;
  68. };
  69. usb3_port2: port@2 {
  70. reg = <2>;
  71. #trigger-source-cells = <0>;
  72. };
  73. };
  74. };
  75. crypto@8e3a000 {
  76. status = "okay";
  77. };
  78. watchdog@b017000 {
  79. status = "okay";
  80. };
  81. ess-switch@c000000 {
  82. status = "okay";
  83. };
  84. edma@c080000 {
  85. status = "okay";
  86. };
  87. };
  88. led_spi {
  89. compatible = "spi-gpio";
  90. #address-cells = <1>;
  91. #size-cells = <0>;
  92. sck-gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
  93. mosi-gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>;
  94. num-chipselects = <0>;
  95. led_gpio: led_gpio@0 {
  96. compatible = "fairchild,74hc595";
  97. reg = <0>;
  98. gpio-controller;
  99. #gpio-cells = <2>;
  100. registers-number = <1>;
  101. spi-max-frequency = <1000000>;
  102. };
  103. };
  104. leds {
  105. compatible = "gpio-leds";
  106. usb {
  107. label = "blue:usb";
  108. gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>;
  109. linux,default-trigger = "usbport";
  110. trigger-sources = <&usb3_port1>, <&usb3_port2>, <&usb2_port1>;
  111. };
  112. led_sys: can {
  113. label = "blue:can";
  114. gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
  115. };
  116. wan {
  117. label = "blue:wan";
  118. gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
  119. };
  120. lan1 {
  121. label = "blue:lan1";
  122. gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
  123. };
  124. lan2 {
  125. label = "blue:lan2";
  126. gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
  127. };
  128. wlan2g {
  129. label = "blue:wlan2g";
  130. gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
  131. linux,default-trigger = "phy0tpt";
  132. };
  133. wlan5g {
  134. label = "blue:wlan5g";
  135. gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
  136. linux,default-trigger = "phy1tpt";
  137. };
  138. };
  139. keys {
  140. compatible = "gpio-keys";
  141. reset {
  142. label = "reset";
  143. gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
  144. linux,code = <KEY_RESTART>;
  145. };
  146. };
  147. };
  148. &blsp_dma {
  149. status = "okay";
  150. };
  151. &blsp1_uart1 {
  152. status = "okay";
  153. };
  154. &blsp1_uart2 {
  155. status = "okay";
  156. };
  157. &cryptobam {
  158. status = "okay";
  159. };
  160. &gmac0 {
  161. nvmem-cells = <&macaddr_art_1006>;
  162. nvmem-cell-names = "mac-address";
  163. };
  164. &gmac1 {
  165. nvmem-cells = <&macaddr_art_5006>;
  166. nvmem-cell-names = "mac-address";
  167. };
  168. &nand {
  169. pinctrl-0 = <&nand_pins>;
  170. pinctrl-names = "default";
  171. status = "okay";
  172. nand@0 {
  173. partitions {
  174. compatible = "fixed-partitions";
  175. #address-cells = <1>;
  176. #size-cells = <1>;
  177. partition@0 {
  178. label = "SBL1";
  179. reg = <0x0 0x100000>;
  180. read-only;
  181. };
  182. partition@100000 {
  183. label = "MIBIB";
  184. reg = <0x100000 0x100000>;
  185. read-only;
  186. };
  187. partition@200000 {
  188. label = "BOOTCONFIG";
  189. reg = <0x200000 0x100000>;
  190. };
  191. partition@300000 {
  192. label = "QSEE";
  193. reg = <0x300000 0x100000>;
  194. read-only;
  195. };
  196. partition@400000 {
  197. label = "QSEE_1";
  198. reg = <0x400000 0x100000>;
  199. read-only;
  200. };
  201. partition@500000 {
  202. label = "CDT";
  203. reg = <0x500000 0x80000>;
  204. read-only;
  205. };
  206. partition@580000 {
  207. label = "CDT_1";
  208. reg = <0x580000 0x80000>;
  209. read-only;
  210. };
  211. partition@600000 {
  212. label = "BOOTCONFIG1";
  213. reg = <0x600000 0x80000>;
  214. };
  215. partition@680000 {
  216. label = "APPSBLENV";
  217. reg = <0x680000 0x80000>;
  218. };
  219. partition@700000 {
  220. label = "APPSBL";
  221. reg = <0x700000 0x200000>;
  222. read-only;
  223. };
  224. partition@900000 {
  225. label = "APPSBL_1";
  226. reg = <0x900000 0x200000>;
  227. read-only;
  228. };
  229. art: partition@b00000 {
  230. label = "ART";
  231. reg = <0xb00000 0x80000>;
  232. read-only;
  233. };
  234. partition@b80000 {
  235. label = "ubi";
  236. reg = <0xb80000 0x7480000>;
  237. };
  238. };
  239. };
  240. };
  241. &qpic_bam {
  242. status = "okay";
  243. };
  244. &tlmm {
  245. mdio_pins: mdio_pinmux {
  246. mux_1 {
  247. pins = "gpio6";
  248. function = "mdio";
  249. bias-pull-up;
  250. };
  251. mux_2 {
  252. pins = "gpio7";
  253. function = "mdc";
  254. bias-pull-up;
  255. };
  256. };
  257. nand_pins: nand_pins {
  258. pullups {
  259. pins = "gpio52", "gpio53", "gpio58",
  260. "gpio59";
  261. function = "qpic";
  262. bias-pull-up;
  263. };
  264. pulldowns {
  265. pins = "gpio54", "gpio55", "gpio56",
  266. "gpio57", "gpio60", "gpio61",
  267. "gpio62", "gpio63", "gpio64",
  268. "gpio65", "gpio66", "gpio67",
  269. "gpio68", "gpio69";
  270. function = "qpic";
  271. bias-pull-down;
  272. };
  273. };
  274. };
  275. &usb3_ss_phy {
  276. status = "okay";
  277. };
  278. &usb3_hs_phy {
  279. status = "okay";
  280. };
  281. &usb2_hs_phy {
  282. status = "okay";
  283. };
  284. &wifi0 {
  285. status = "okay";
  286. qcom,ath10k-calibration-variant = "CM520-79F";
  287. };
  288. &wifi1 {
  289. status = "okay";
  290. qcom,ath10k-calibration-variant = "CM520-79F";
  291. };
  292. &art {
  293. compatible = "nvmem-cells";
  294. #address-cells = <1>;
  295. #size-cells = <1>;
  296. macaddr_art_1006: macaddr@1006 {
  297. reg = <0x1006 0x6>;
  298. };
  299. macaddr_art_5006: macaddr@5006 {
  300. reg = <0x5006 0x6>;
  301. };
  302. };