715-03-v6.2-net-dpaa-Convert-to-phylink.patch 72 KB

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  1. From 38e50fc3d43882a43115b4f1ca3eb88255163c5b Mon Sep 17 00:00:00 2001
  2. From: Sean Anderson <[email protected]>
  3. Date: Mon, 17 Oct 2022 16:22:38 -0400
  4. Subject: [PATCH 03/21] net: dpaa: Convert to phylink
  5. This converts DPAA to phylink. All macs are converted. This should work
  6. with no device tree modifications (including those made in this series),
  7. except for QSGMII (as noted previously).
  8. The mEMAC configuration is one of the tricker areas. I have tried to
  9. capture all the restrictions across the various models. Most of the time,
  10. we assume that if the serdes supports a mode or the phy-interface-mode
  11. specifies it, then we support it. The only place we can't do this is
  12. (RG)MII, since there's no serdes. In that case, we rely on a (new)
  13. devicetree property. There are also several cases where half-duplex is
  14. broken. Unfortunately, only a single compatible is used for the MAC, so we
  15. have to use the board compatible instead.
  16. The 10GEC conversion is very straightforward, since it only supports XAUI.
  17. There is generally nothing to configure.
  18. The dTSEC conversion is broadly similar to mEMAC, but is simpler because we
  19. don't support configuring the SerDes (though this can be easily added) and
  20. we don't have multiple PCSs. From what I can tell, there's nothing
  21. different in the driver or documentation between SGMII and 1000BASE-X
  22. except for the advertising. Similarly, I couldn't find anything about
  23. 2500BASE-X. In both cases, I treat them like SGMII. These modes aren't used
  24. by any in-tree boards. Similarly, despite being mentioned in the driver, I
  25. couldn't find any documented SoCs which supported QSGMII. I have left it
  26. unimplemented for now.
  27. Signed-off-by: Sean Anderson <[email protected]>
  28. Signed-off-by: David S. Miller <[email protected]>
  29. ---
  30. drivers/net/ethernet/freescale/dpaa/Kconfig | 4 +-
  31. .../net/ethernet/freescale/dpaa/dpaa_eth.c | 89 +--
  32. .../ethernet/freescale/dpaa/dpaa_ethtool.c | 90 +--
  33. drivers/net/ethernet/freescale/fman/Kconfig | 1 -
  34. .../net/ethernet/freescale/fman/fman_dtsec.c | 458 +++++++--------
  35. .../net/ethernet/freescale/fman/fman_mac.h | 10 -
  36. .../net/ethernet/freescale/fman/fman_memac.c | 547 +++++++++---------
  37. .../net/ethernet/freescale/fman/fman_tgec.c | 131 ++---
  38. drivers/net/ethernet/freescale/fman/mac.c | 168 +-----
  39. drivers/net/ethernet/freescale/fman/mac.h | 23 +-
  40. 10 files changed, 612 insertions(+), 909 deletions(-)
  41. --- a/drivers/net/ethernet/freescale/dpaa/Kconfig
  42. +++ b/drivers/net/ethernet/freescale/dpaa/Kconfig
  43. @@ -2,8 +2,8 @@
  44. menuconfig FSL_DPAA_ETH
  45. tristate "DPAA Ethernet"
  46. depends on FSL_DPAA && FSL_FMAN
  47. - select PHYLIB
  48. - select FIXED_PHY
  49. + select PHYLINK
  50. + select PCS_LYNX
  51. help
  52. Data Path Acceleration Architecture Ethernet driver,
  53. supporting the Freescale QorIQ chips.
  54. --- a/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
  55. +++ b/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
  56. @@ -264,8 +264,19 @@ static int dpaa_netdev_init(struct net_d
  57. net_dev->needed_headroom = priv->tx_headroom;
  58. net_dev->watchdog_timeo = msecs_to_jiffies(tx_timeout);
  59. - mac_dev->net_dev = net_dev;
  60. + /* The rest of the config is filled in by the mac device already */
  61. + mac_dev->phylink_config.dev = &net_dev->dev;
  62. + mac_dev->phylink_config.type = PHYLINK_NETDEV;
  63. mac_dev->update_speed = dpaa_eth_cgr_set_speed;
  64. + mac_dev->phylink = phylink_create(&mac_dev->phylink_config,
  65. + dev_fwnode(mac_dev->dev),
  66. + mac_dev->phy_if,
  67. + mac_dev->phylink_ops);
  68. + if (IS_ERR(mac_dev->phylink)) {
  69. + err = PTR_ERR(mac_dev->phylink);
  70. + dev_err_probe(dev, err, "Could not create phylink\n");
  71. + return err;
  72. + }
  73. /* start without the RUNNING flag, phylib controls it later */
  74. netif_carrier_off(net_dev);
  75. @@ -273,6 +284,7 @@ static int dpaa_netdev_init(struct net_d
  76. err = register_netdev(net_dev);
  77. if (err < 0) {
  78. dev_err(dev, "register_netdev() = %d\n", err);
  79. + phylink_destroy(mac_dev->phylink);
  80. return err;
  81. }
  82. @@ -295,8 +307,7 @@ static int dpaa_stop(struct net_device *
  83. */
  84. msleep(200);
  85. - if (mac_dev->phy_dev)
  86. - phy_stop(mac_dev->phy_dev);
  87. + phylink_stop(mac_dev->phylink);
  88. mac_dev->disable(mac_dev->fman_mac);
  89. for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) {
  90. @@ -305,8 +316,7 @@ static int dpaa_stop(struct net_device *
  91. err = error;
  92. }
  93. - if (net_dev->phydev)
  94. - phy_disconnect(net_dev->phydev);
  95. + phylink_disconnect_phy(mac_dev->phylink);
  96. net_dev->phydev = NULL;
  97. msleep(200);
  98. @@ -834,10 +844,10 @@ static int dpaa_eth_cgr_init(struct dpaa
  99. /* Set different thresholds based on the configured MAC speed.
  100. * This may turn suboptimal if the MAC is reconfigured at another
  101. - * speed, so MACs must call dpaa_eth_cgr_set_speed in their adjust_link
  102. + * speed, so MACs must call dpaa_eth_cgr_set_speed in their link_up
  103. * callback.
  104. */
  105. - if (priv->mac_dev->if_support & SUPPORTED_10000baseT_Full)
  106. + if (priv->mac_dev->phylink_config.mac_capabilities & MAC_10000FD)
  107. cs_th = DPAA_CS_THRESHOLD_10G;
  108. else
  109. cs_th = DPAA_CS_THRESHOLD_1G;
  110. @@ -866,7 +876,7 @@ out_error:
  111. static void dpaa_eth_cgr_set_speed(struct mac_device *mac_dev, int speed)
  112. {
  113. - struct net_device *net_dev = mac_dev->net_dev;
  114. + struct net_device *net_dev = to_net_dev(mac_dev->phylink_config.dev);
  115. struct dpaa_priv *priv = netdev_priv(net_dev);
  116. struct qm_mcc_initcgr opts = { };
  117. u32 cs_th;
  118. @@ -2905,58 +2915,6 @@ static void dpaa_eth_napi_disable(struct
  119. }
  120. }
  121. -static void dpaa_adjust_link(struct net_device *net_dev)
  122. -{
  123. - struct mac_device *mac_dev;
  124. - struct dpaa_priv *priv;
  125. -
  126. - priv = netdev_priv(net_dev);
  127. - mac_dev = priv->mac_dev;
  128. - mac_dev->adjust_link(mac_dev);
  129. -}
  130. -
  131. -/* The Aquantia PHYs are capable of performing rate adaptation */
  132. -#define PHY_VEND_AQUANTIA 0x03a1b400
  133. -#define PHY_VEND_AQUANTIA2 0x31c31c00
  134. -
  135. -static int dpaa_phy_init(struct net_device *net_dev)
  136. -{
  137. - __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
  138. - struct mac_device *mac_dev;
  139. - struct phy_device *phy_dev;
  140. - struct dpaa_priv *priv;
  141. - u32 phy_vendor;
  142. -
  143. - priv = netdev_priv(net_dev);
  144. - mac_dev = priv->mac_dev;
  145. -
  146. - phy_dev = of_phy_connect(net_dev, mac_dev->phy_node,
  147. - &dpaa_adjust_link, 0,
  148. - mac_dev->phy_if);
  149. - if (!phy_dev) {
  150. - netif_err(priv, ifup, net_dev, "init_phy() failed\n");
  151. - return -ENODEV;
  152. - }
  153. -
  154. - phy_vendor = phy_dev->drv->phy_id & GENMASK(31, 10);
  155. - /* Unless the PHY is capable of rate adaptation */
  156. - if (mac_dev->phy_if != PHY_INTERFACE_MODE_XGMII ||
  157. - (phy_vendor != PHY_VEND_AQUANTIA &&
  158. - phy_vendor != PHY_VEND_AQUANTIA2)) {
  159. - /* remove any features not supported by the controller */
  160. - ethtool_convert_legacy_u32_to_link_mode(mask,
  161. - mac_dev->if_support);
  162. - linkmode_and(phy_dev->supported, phy_dev->supported, mask);
  163. - }
  164. -
  165. - phy_support_asym_pause(phy_dev);
  166. -
  167. - mac_dev->phy_dev = phy_dev;
  168. - net_dev->phydev = phy_dev;
  169. -
  170. - return 0;
  171. -}
  172. -
  173. static int dpaa_open(struct net_device *net_dev)
  174. {
  175. struct mac_device *mac_dev;
  176. @@ -2967,7 +2925,8 @@ static int dpaa_open(struct net_device *
  177. mac_dev = priv->mac_dev;
  178. dpaa_eth_napi_enable(priv);
  179. - err = dpaa_phy_init(net_dev);
  180. + err = phylink_of_phy_connect(mac_dev->phylink,
  181. + mac_dev->dev->of_node, 0);
  182. if (err)
  183. goto phy_init_failed;
  184. @@ -2982,7 +2941,7 @@ static int dpaa_open(struct net_device *
  185. netif_err(priv, ifup, net_dev, "mac_dev->enable() = %d\n", err);
  186. goto mac_start_failed;
  187. }
  188. - phy_start(priv->mac_dev->phy_dev);
  189. + phylink_start(mac_dev->phylink);
  190. netif_tx_start_all_queues(net_dev);
  191. @@ -2991,6 +2950,7 @@ static int dpaa_open(struct net_device *
  192. mac_start_failed:
  193. for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++)
  194. fman_port_disable(mac_dev->port[i]);
  195. + phylink_disconnect_phy(mac_dev->phylink);
  196. phy_init_failed:
  197. dpaa_eth_napi_disable(priv);
  198. @@ -3146,10 +3106,12 @@ static int dpaa_ts_ioctl(struct net_devi
  199. static int dpaa_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd)
  200. {
  201. int ret = -EINVAL;
  202. + struct dpaa_priv *priv = netdev_priv(net_dev);
  203. if (cmd == SIOCGMIIREG) {
  204. if (net_dev->phydev)
  205. - return phy_mii_ioctl(net_dev->phydev, rq, cmd);
  206. + return phylink_mii_ioctl(priv->mac_dev->phylink, rq,
  207. + cmd);
  208. }
  209. if (cmd == SIOCSHWTSTAMP)
  210. @@ -3552,6 +3514,7 @@ static int dpaa_remove(struct platform_d
  211. dev_set_drvdata(dev, NULL);
  212. unregister_netdev(net_dev);
  213. + phylink_destroy(priv->mac_dev->phylink);
  214. err = dpaa_fq_free(dev, &priv->dpaa_fq_list);
  215. --- a/drivers/net/ethernet/freescale/dpaa/dpaa_ethtool.c
  216. +++ b/drivers/net/ethernet/freescale/dpaa/dpaa_ethtool.c
  217. @@ -54,27 +54,19 @@ static char dpaa_stats_global[][ETH_GSTR
  218. static int dpaa_get_link_ksettings(struct net_device *net_dev,
  219. struct ethtool_link_ksettings *cmd)
  220. {
  221. - if (!net_dev->phydev)
  222. - return 0;
  223. + struct dpaa_priv *priv = netdev_priv(net_dev);
  224. + struct mac_device *mac_dev = priv->mac_dev;
  225. - phy_ethtool_ksettings_get(net_dev->phydev, cmd);
  226. -
  227. - return 0;
  228. + return phylink_ethtool_ksettings_get(mac_dev->phylink, cmd);
  229. }
  230. static int dpaa_set_link_ksettings(struct net_device *net_dev,
  231. const struct ethtool_link_ksettings *cmd)
  232. {
  233. - int err;
  234. -
  235. - if (!net_dev->phydev)
  236. - return -ENODEV;
  237. + struct dpaa_priv *priv = netdev_priv(net_dev);
  238. + struct mac_device *mac_dev = priv->mac_dev;
  239. - err = phy_ethtool_ksettings_set(net_dev->phydev, cmd);
  240. - if (err < 0)
  241. - netdev_err(net_dev, "phy_ethtool_ksettings_set() = %d\n", err);
  242. -
  243. - return err;
  244. + return phylink_ethtool_ksettings_set(mac_dev->phylink, cmd);
  245. }
  246. static void dpaa_get_drvinfo(struct net_device *net_dev,
  247. @@ -99,80 +91,28 @@ static void dpaa_set_msglevel(struct net
  248. static int dpaa_nway_reset(struct net_device *net_dev)
  249. {
  250. - int err;
  251. -
  252. - if (!net_dev->phydev)
  253. - return -ENODEV;
  254. + struct dpaa_priv *priv = netdev_priv(net_dev);
  255. + struct mac_device *mac_dev = priv->mac_dev;
  256. - err = 0;
  257. - if (net_dev->phydev->autoneg) {
  258. - err = phy_start_aneg(net_dev->phydev);
  259. - if (err < 0)
  260. - netdev_err(net_dev, "phy_start_aneg() = %d\n",
  261. - err);
  262. - }
  263. -
  264. - return err;
  265. + return phylink_ethtool_nway_reset(mac_dev->phylink);
  266. }
  267. static void dpaa_get_pauseparam(struct net_device *net_dev,
  268. struct ethtool_pauseparam *epause)
  269. {
  270. - struct mac_device *mac_dev;
  271. - struct dpaa_priv *priv;
  272. -
  273. - priv = netdev_priv(net_dev);
  274. - mac_dev = priv->mac_dev;
  275. -
  276. - if (!net_dev->phydev)
  277. - return;
  278. + struct dpaa_priv *priv = netdev_priv(net_dev);
  279. + struct mac_device *mac_dev = priv->mac_dev;
  280. - epause->autoneg = mac_dev->autoneg_pause;
  281. - epause->rx_pause = mac_dev->rx_pause_active;
  282. - epause->tx_pause = mac_dev->tx_pause_active;
  283. + phylink_ethtool_get_pauseparam(mac_dev->phylink, epause);
  284. }
  285. static int dpaa_set_pauseparam(struct net_device *net_dev,
  286. struct ethtool_pauseparam *epause)
  287. {
  288. - struct mac_device *mac_dev;
  289. - struct phy_device *phydev;
  290. - bool rx_pause, tx_pause;
  291. - struct dpaa_priv *priv;
  292. - int err;
  293. -
  294. - priv = netdev_priv(net_dev);
  295. - mac_dev = priv->mac_dev;
  296. -
  297. - phydev = net_dev->phydev;
  298. - if (!phydev) {
  299. - netdev_err(net_dev, "phy device not initialized\n");
  300. - return -ENODEV;
  301. - }
  302. -
  303. - if (!phy_validate_pause(phydev, epause))
  304. - return -EINVAL;
  305. -
  306. - /* The MAC should know how to handle PAUSE frame autonegotiation before
  307. - * adjust_link is triggered by a forced renegotiation of sym/asym PAUSE
  308. - * settings.
  309. - */
  310. - mac_dev->autoneg_pause = !!epause->autoneg;
  311. - mac_dev->rx_pause_req = !!epause->rx_pause;
  312. - mac_dev->tx_pause_req = !!epause->tx_pause;
  313. -
  314. - /* Determine the sym/asym advertised PAUSE capabilities from the desired
  315. - * rx/tx pause settings.
  316. - */
  317. -
  318. - phy_set_asym_pause(phydev, epause->rx_pause, epause->tx_pause);
  319. -
  320. - fman_get_pause_cfg(mac_dev, &rx_pause, &tx_pause);
  321. - err = fman_set_mac_active_pause(mac_dev, rx_pause, tx_pause);
  322. - if (err < 0)
  323. - netdev_err(net_dev, "set_mac_active_pause() = %d\n", err);
  324. + struct dpaa_priv *priv = netdev_priv(net_dev);
  325. + struct mac_device *mac_dev = priv->mac_dev;
  326. - return err;
  327. + return phylink_ethtool_set_pauseparam(mac_dev->phylink, epause);
  328. }
  329. static int dpaa_get_sset_count(struct net_device *net_dev, int type)
  330. --- a/drivers/net/ethernet/freescale/fman/Kconfig
  331. +++ b/drivers/net/ethernet/freescale/fman/Kconfig
  332. @@ -3,7 +3,6 @@ config FSL_FMAN
  333. tristate "FMan support"
  334. depends on FSL_SOC || ARCH_LAYERSCAPE || COMPILE_TEST
  335. select GENERIC_ALLOCATOR
  336. - select PHYLIB
  337. select PHYLINK
  338. select PCS
  339. select PCS_LYNX
  340. --- a/drivers/net/ethernet/freescale/fman/fman_dtsec.c
  341. +++ b/drivers/net/ethernet/freescale/fman/fman_dtsec.c
  342. @@ -17,6 +17,7 @@
  343. #include <linux/crc32.h>
  344. #include <linux/of_mdio.h>
  345. #include <linux/mii.h>
  346. +#include <linux/netdevice.h>
  347. /* TBI register addresses */
  348. #define MII_TBICON 0x11
  349. @@ -29,9 +30,6 @@
  350. #define TBICON_CLK_SELECT 0x0020 /* Clock select */
  351. #define TBICON_MI_MODE 0x0010 /* GMII mode (TBI if not set) */
  352. -#define TBIANA_SGMII 0x4001
  353. -#define TBIANA_1000X 0x01a0
  354. -
  355. /* Interrupt Mask Register (IMASK) */
  356. #define DTSEC_IMASK_BREN 0x80000000
  357. #define DTSEC_IMASK_RXCEN 0x40000000
  358. @@ -92,9 +90,10 @@
  359. #define DTSEC_ECNTRL_GMIIM 0x00000040
  360. #define DTSEC_ECNTRL_TBIM 0x00000020
  361. -#define DTSEC_ECNTRL_SGMIIM 0x00000002
  362. #define DTSEC_ECNTRL_RPM 0x00000010
  363. #define DTSEC_ECNTRL_R100M 0x00000008
  364. +#define DTSEC_ECNTRL_RMM 0x00000004
  365. +#define DTSEC_ECNTRL_SGMIIM 0x00000002
  366. #define DTSEC_ECNTRL_QSGMIIM 0x00000001
  367. #define TCTRL_TTSE 0x00000040
  368. @@ -318,7 +317,8 @@ struct fman_mac {
  369. void *fm;
  370. struct fman_rev_info fm_rev_info;
  371. bool basex_if;
  372. - struct phy_device *tbiphy;
  373. + struct mdio_device *tbidev;
  374. + struct phylink_pcs pcs;
  375. };
  376. static void set_dflts(struct dtsec_cfg *cfg)
  377. @@ -356,56 +356,14 @@ static int init(struct dtsec_regs __iome
  378. phy_interface_t iface, u16 iface_speed, u64 addr,
  379. u32 exception_mask, u8 tbi_addr)
  380. {
  381. - bool is_rgmii, is_sgmii, is_qsgmii;
  382. enet_addr_t eth_addr;
  383. - u32 tmp;
  384. + u32 tmp = 0;
  385. int i;
  386. /* Soft reset */
  387. iowrite32be(MACCFG1_SOFT_RESET, &regs->maccfg1);
  388. iowrite32be(0, &regs->maccfg1);
  389. - /* dtsec_id2 */
  390. - tmp = ioread32be(&regs->tsec_id2);
  391. -
  392. - /* check RGMII support */
  393. - if (iface == PHY_INTERFACE_MODE_RGMII ||
  394. - iface == PHY_INTERFACE_MODE_RGMII_ID ||
  395. - iface == PHY_INTERFACE_MODE_RGMII_RXID ||
  396. - iface == PHY_INTERFACE_MODE_RGMII_TXID ||
  397. - iface == PHY_INTERFACE_MODE_RMII)
  398. - if (tmp & DTSEC_ID2_INT_REDUCED_OFF)
  399. - return -EINVAL;
  400. -
  401. - if (iface == PHY_INTERFACE_MODE_SGMII ||
  402. - iface == PHY_INTERFACE_MODE_MII)
  403. - if (tmp & DTSEC_ID2_INT_REDUCED_OFF)
  404. - return -EINVAL;
  405. -
  406. - is_rgmii = iface == PHY_INTERFACE_MODE_RGMII ||
  407. - iface == PHY_INTERFACE_MODE_RGMII_ID ||
  408. - iface == PHY_INTERFACE_MODE_RGMII_RXID ||
  409. - iface == PHY_INTERFACE_MODE_RGMII_TXID;
  410. - is_sgmii = iface == PHY_INTERFACE_MODE_SGMII;
  411. - is_qsgmii = iface == PHY_INTERFACE_MODE_QSGMII;
  412. -
  413. - tmp = 0;
  414. - if (is_rgmii || iface == PHY_INTERFACE_MODE_GMII)
  415. - tmp |= DTSEC_ECNTRL_GMIIM;
  416. - if (is_sgmii)
  417. - tmp |= (DTSEC_ECNTRL_SGMIIM | DTSEC_ECNTRL_TBIM);
  418. - if (is_qsgmii)
  419. - tmp |= (DTSEC_ECNTRL_SGMIIM | DTSEC_ECNTRL_TBIM |
  420. - DTSEC_ECNTRL_QSGMIIM);
  421. - if (is_rgmii)
  422. - tmp |= DTSEC_ECNTRL_RPM;
  423. - if (iface_speed == SPEED_100)
  424. - tmp |= DTSEC_ECNTRL_R100M;
  425. -
  426. - iowrite32be(tmp, &regs->ecntrl);
  427. -
  428. - tmp = 0;
  429. -
  430. if (cfg->tx_pause_time)
  431. tmp |= cfg->tx_pause_time;
  432. if (cfg->tx_pause_time_extd)
  433. @@ -446,17 +404,10 @@ static int init(struct dtsec_regs __iome
  434. tmp = 0;
  435. - if (iface_speed < SPEED_1000)
  436. - tmp |= MACCFG2_NIBBLE_MODE;
  437. - else if (iface_speed == SPEED_1000)
  438. - tmp |= MACCFG2_BYTE_MODE;
  439. -
  440. tmp |= (cfg->preamble_len << MACCFG2_PREAMBLE_LENGTH_SHIFT) &
  441. MACCFG2_PREAMBLE_LENGTH_MASK;
  442. if (cfg->tx_pad_crc)
  443. tmp |= MACCFG2_PAD_CRC_EN;
  444. - /* Full Duplex */
  445. - tmp |= MACCFG2_FULL_DUPLEX;
  446. iowrite32be(tmp, &regs->maccfg2);
  447. tmp = (((cfg->non_back_to_back_ipg1 <<
  448. @@ -525,10 +476,6 @@ static void set_bucket(struct dtsec_regs
  449. static int check_init_parameters(struct fman_mac *dtsec)
  450. {
  451. - if (dtsec->max_speed >= SPEED_10000) {
  452. - pr_err("1G MAC driver supports 1G or lower speeds\n");
  453. - return -EINVAL;
  454. - }
  455. if ((dtsec->dtsec_drv_param)->rx_prepend >
  456. MAX_PACKET_ALIGNMENT) {
  457. pr_err("packetAlignmentPadding can't be > than %d\n",
  458. @@ -630,22 +577,10 @@ static int get_exception_flag(enum fman_
  459. return bit_mask;
  460. }
  461. -static bool is_init_done(struct dtsec_cfg *dtsec_drv_params)
  462. -{
  463. - /* Checks if dTSEC driver parameters were initialized */
  464. - if (!dtsec_drv_params)
  465. - return true;
  466. -
  467. - return false;
  468. -}
  469. -
  470. static u16 dtsec_get_max_frame_length(struct fman_mac *dtsec)
  471. {
  472. struct dtsec_regs __iomem *regs = dtsec->regs;
  473. - if (is_init_done(dtsec->dtsec_drv_param))
  474. - return 0;
  475. -
  476. return (u16)ioread32be(&regs->maxfrm);
  477. }
  478. @@ -682,6 +617,7 @@ static void dtsec_isr(void *handle)
  479. dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_COL_RET_LMT);
  480. if (event & DTSEC_IMASK_XFUNEN) {
  481. /* FM_TX_LOCKUP_ERRATA_DTSEC6 Errata workaround */
  482. + /* FIXME: This races with the rest of the driver! */
  483. if (dtsec->fm_rev_info.major == 2) {
  484. u32 tpkt1, tmp_reg1, tpkt2, tmp_reg2, i;
  485. /* a. Write 0x00E0_0C00 to DTSEC_ID
  486. @@ -814,6 +750,43 @@ static void free_init_resources(struct f
  487. dtsec->unicast_addr_hash = NULL;
  488. }
  489. +static struct fman_mac *pcs_to_dtsec(struct phylink_pcs *pcs)
  490. +{
  491. + return container_of(pcs, struct fman_mac, pcs);
  492. +}
  493. +
  494. +static void dtsec_pcs_get_state(struct phylink_pcs *pcs,
  495. + struct phylink_link_state *state)
  496. +{
  497. + struct fman_mac *dtsec = pcs_to_dtsec(pcs);
  498. +
  499. + phylink_mii_c22_pcs_get_state(dtsec->tbidev, state);
  500. +}
  501. +
  502. +static int dtsec_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
  503. + phy_interface_t interface,
  504. + const unsigned long *advertising,
  505. + bool permit_pause_to_mac)
  506. +{
  507. + struct fman_mac *dtsec = pcs_to_dtsec(pcs);
  508. +
  509. + return phylink_mii_c22_pcs_config(dtsec->tbidev, mode, interface,
  510. + advertising);
  511. +}
  512. +
  513. +static void dtsec_pcs_an_restart(struct phylink_pcs *pcs)
  514. +{
  515. + struct fman_mac *dtsec = pcs_to_dtsec(pcs);
  516. +
  517. + phylink_mii_c22_pcs_an_restart(dtsec->tbidev);
  518. +}
  519. +
  520. +static const struct phylink_pcs_ops dtsec_pcs_ops = {
  521. + .pcs_get_state = dtsec_pcs_get_state,
  522. + .pcs_config = dtsec_pcs_config,
  523. + .pcs_an_restart = dtsec_pcs_an_restart,
  524. +};
  525. +
  526. static void graceful_start(struct fman_mac *dtsec)
  527. {
  528. struct dtsec_regs __iomem *regs = dtsec->regs;
  529. @@ -854,36 +827,11 @@ static void graceful_stop(struct fman_ma
  530. static int dtsec_enable(struct fman_mac *dtsec)
  531. {
  532. - struct dtsec_regs __iomem *regs = dtsec->regs;
  533. - u32 tmp;
  534. -
  535. - if (!is_init_done(dtsec->dtsec_drv_param))
  536. - return -EINVAL;
  537. -
  538. - /* Enable */
  539. - tmp = ioread32be(&regs->maccfg1);
  540. - tmp |= MACCFG1_RX_EN | MACCFG1_TX_EN;
  541. - iowrite32be(tmp, &regs->maccfg1);
  542. -
  543. - /* Graceful start - clear the graceful Rx/Tx stop bit */
  544. - graceful_start(dtsec);
  545. -
  546. return 0;
  547. }
  548. static void dtsec_disable(struct fman_mac *dtsec)
  549. {
  550. - struct dtsec_regs __iomem *regs = dtsec->regs;
  551. - u32 tmp;
  552. -
  553. - WARN_ON_ONCE(!is_init_done(dtsec->dtsec_drv_param));
  554. -
  555. - /* Graceful stop - Assert the graceful Rx/Tx stop bit */
  556. - graceful_stop(dtsec);
  557. -
  558. - tmp = ioread32be(&regs->maccfg1);
  559. - tmp &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
  560. - iowrite32be(tmp, &regs->maccfg1);
  561. }
  562. static int dtsec_set_tx_pause_frames(struct fman_mac *dtsec,
  563. @@ -894,11 +842,6 @@ static int dtsec_set_tx_pause_frames(str
  564. struct dtsec_regs __iomem *regs = dtsec->regs;
  565. u32 ptv = 0;
  566. - if (!is_init_done(dtsec->dtsec_drv_param))
  567. - return -EINVAL;
  568. -
  569. - graceful_stop(dtsec);
  570. -
  571. if (pause_time) {
  572. /* FM_BAD_TX_TS_IN_B_2_B_ERRATA_DTSEC_A003 Errata workaround */
  573. if (dtsec->fm_rev_info.major == 2 && pause_time <= 320) {
  574. @@ -919,8 +862,6 @@ static int dtsec_set_tx_pause_frames(str
  575. iowrite32be(ioread32be(&regs->maccfg1) & ~MACCFG1_TX_FLOW,
  576. &regs->maccfg1);
  577. - graceful_start(dtsec);
  578. -
  579. return 0;
  580. }
  581. @@ -929,11 +870,6 @@ static int dtsec_accept_rx_pause_frames(
  582. struct dtsec_regs __iomem *regs = dtsec->regs;
  583. u32 tmp;
  584. - if (!is_init_done(dtsec->dtsec_drv_param))
  585. - return -EINVAL;
  586. -
  587. - graceful_stop(dtsec);
  588. -
  589. tmp = ioread32be(&regs->maccfg1);
  590. if (en)
  591. tmp |= MACCFG1_RX_FLOW;
  592. @@ -941,17 +877,125 @@ static int dtsec_accept_rx_pause_frames(
  593. tmp &= ~MACCFG1_RX_FLOW;
  594. iowrite32be(tmp, &regs->maccfg1);
  595. + return 0;
  596. +}
  597. +
  598. +static struct phylink_pcs *dtsec_select_pcs(struct phylink_config *config,
  599. + phy_interface_t iface)
  600. +{
  601. + struct fman_mac *dtsec = fman_config_to_mac(config)->fman_mac;
  602. +
  603. + switch (iface) {
  604. + case PHY_INTERFACE_MODE_SGMII:
  605. + case PHY_INTERFACE_MODE_1000BASEX:
  606. + case PHY_INTERFACE_MODE_2500BASEX:
  607. + return &dtsec->pcs;
  608. + default:
  609. + return NULL;
  610. + }
  611. +}
  612. +
  613. +static void dtsec_mac_config(struct phylink_config *config, unsigned int mode,
  614. + const struct phylink_link_state *state)
  615. +{
  616. + struct mac_device *mac_dev = fman_config_to_mac(config);
  617. + struct dtsec_regs __iomem *regs = mac_dev->fman_mac->regs;
  618. + u32 tmp;
  619. +
  620. + switch (state->interface) {
  621. + case PHY_INTERFACE_MODE_RMII:
  622. + tmp = DTSEC_ECNTRL_RMM;
  623. + break;
  624. + case PHY_INTERFACE_MODE_RGMII:
  625. + case PHY_INTERFACE_MODE_RGMII_ID:
  626. + case PHY_INTERFACE_MODE_RGMII_RXID:
  627. + case PHY_INTERFACE_MODE_RGMII_TXID:
  628. + tmp = DTSEC_ECNTRL_GMIIM | DTSEC_ECNTRL_RPM;
  629. + break;
  630. + case PHY_INTERFACE_MODE_SGMII:
  631. + case PHY_INTERFACE_MODE_1000BASEX:
  632. + case PHY_INTERFACE_MODE_2500BASEX:
  633. + tmp = DTSEC_ECNTRL_TBIM | DTSEC_ECNTRL_SGMIIM;
  634. + break;
  635. + default:
  636. + dev_warn(mac_dev->dev, "cannot configure dTSEC for %s\n",
  637. + phy_modes(state->interface));
  638. + return;
  639. + }
  640. +
  641. + iowrite32be(tmp, &regs->ecntrl);
  642. +}
  643. +
  644. +static void dtsec_link_up(struct phylink_config *config, struct phy_device *phy,
  645. + unsigned int mode, phy_interface_t interface,
  646. + int speed, int duplex, bool tx_pause, bool rx_pause)
  647. +{
  648. + struct mac_device *mac_dev = fman_config_to_mac(config);
  649. + struct fman_mac *dtsec = mac_dev->fman_mac;
  650. + struct dtsec_regs __iomem *regs = dtsec->regs;
  651. + u16 pause_time = tx_pause ? FSL_FM_PAUSE_TIME_ENABLE :
  652. + FSL_FM_PAUSE_TIME_DISABLE;
  653. + u32 tmp;
  654. +
  655. + dtsec_set_tx_pause_frames(dtsec, 0, pause_time, 0);
  656. + dtsec_accept_rx_pause_frames(dtsec, rx_pause);
  657. +
  658. + tmp = ioread32be(&regs->ecntrl);
  659. + if (speed == SPEED_100)
  660. + tmp |= DTSEC_ECNTRL_R100M;
  661. + else
  662. + tmp &= ~DTSEC_ECNTRL_R100M;
  663. + iowrite32be(tmp, &regs->ecntrl);
  664. +
  665. + tmp = ioread32be(&regs->maccfg2);
  666. + tmp &= ~(MACCFG2_NIBBLE_MODE | MACCFG2_BYTE_MODE | MACCFG2_FULL_DUPLEX);
  667. + if (speed >= SPEED_1000)
  668. + tmp |= MACCFG2_BYTE_MODE;
  669. + else
  670. + tmp |= MACCFG2_NIBBLE_MODE;
  671. +
  672. + if (duplex == DUPLEX_FULL)
  673. + tmp |= MACCFG2_FULL_DUPLEX;
  674. +
  675. + iowrite32be(tmp, &regs->maccfg2);
  676. +
  677. + mac_dev->update_speed(mac_dev, speed);
  678. +
  679. + /* Enable */
  680. + tmp = ioread32be(&regs->maccfg1);
  681. + tmp |= MACCFG1_RX_EN | MACCFG1_TX_EN;
  682. + iowrite32be(tmp, &regs->maccfg1);
  683. +
  684. + /* Graceful start - clear the graceful Rx/Tx stop bit */
  685. graceful_start(dtsec);
  686. +}
  687. - return 0;
  688. +static void dtsec_link_down(struct phylink_config *config, unsigned int mode,
  689. + phy_interface_t interface)
  690. +{
  691. + struct fman_mac *dtsec = fman_config_to_mac(config)->fman_mac;
  692. + struct dtsec_regs __iomem *regs = dtsec->regs;
  693. + u32 tmp;
  694. +
  695. + /* Graceful stop - Assert the graceful Rx/Tx stop bit */
  696. + graceful_stop(dtsec);
  697. +
  698. + tmp = ioread32be(&regs->maccfg1);
  699. + tmp &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
  700. + iowrite32be(tmp, &regs->maccfg1);
  701. }
  702. +static const struct phylink_mac_ops dtsec_mac_ops = {
  703. + .validate = phylink_generic_validate,
  704. + .mac_select_pcs = dtsec_select_pcs,
  705. + .mac_config = dtsec_mac_config,
  706. + .mac_link_up = dtsec_link_up,
  707. + .mac_link_down = dtsec_link_down,
  708. +};
  709. +
  710. static int dtsec_modify_mac_address(struct fman_mac *dtsec,
  711. const enet_addr_t *enet_addr)
  712. {
  713. - if (!is_init_done(dtsec->dtsec_drv_param))
  714. - return -EINVAL;
  715. -
  716. graceful_stop(dtsec);
  717. /* Initialize MAC Station Address registers (1 & 2)
  718. @@ -975,9 +1019,6 @@ static int dtsec_add_hash_mac_address(st
  719. u32 crc = 0xFFFFFFFF;
  720. bool mcast, ghtx;
  721. - if (!is_init_done(dtsec->dtsec_drv_param))
  722. - return -EINVAL;
  723. -
  724. addr = ENET_ADDR_TO_UINT64(*eth_addr);
  725. ghtx = (bool)((ioread32be(&regs->rctrl) & RCTRL_GHTX) ? true : false);
  726. @@ -1037,9 +1078,6 @@ static int dtsec_set_allmulti(struct fma
  727. u32 tmp;
  728. struct dtsec_regs __iomem *regs = dtsec->regs;
  729. - if (!is_init_done(dtsec->dtsec_drv_param))
  730. - return -EINVAL;
  731. -
  732. tmp = ioread32be(&regs->rctrl);
  733. if (enable)
  734. tmp |= RCTRL_MPROM;
  735. @@ -1056,9 +1094,6 @@ static int dtsec_set_tstamp(struct fman_
  736. struct dtsec_regs __iomem *regs = dtsec->regs;
  737. u32 rctrl, tctrl;
  738. - if (!is_init_done(dtsec->dtsec_drv_param))
  739. - return -EINVAL;
  740. -
  741. rctrl = ioread32be(&regs->rctrl);
  742. tctrl = ioread32be(&regs->tctrl);
  743. @@ -1087,9 +1122,6 @@ static int dtsec_del_hash_mac_address(st
  744. u32 crc = 0xFFFFFFFF;
  745. bool mcast, ghtx;
  746. - if (!is_init_done(dtsec->dtsec_drv_param))
  747. - return -EINVAL;
  748. -
  749. addr = ENET_ADDR_TO_UINT64(*eth_addr);
  750. ghtx = (bool)((ioread32be(&regs->rctrl) & RCTRL_GHTX) ? true : false);
  751. @@ -1153,9 +1185,6 @@ static int dtsec_set_promiscuous(struct
  752. struct dtsec_regs __iomem *regs = dtsec->regs;
  753. u32 tmp;
  754. - if (!is_init_done(dtsec->dtsec_drv_param))
  755. - return -EINVAL;
  756. -
  757. /* Set unicast promiscuous */
  758. tmp = ioread32be(&regs->rctrl);
  759. if (new_val)
  760. @@ -1177,90 +1206,12 @@ static int dtsec_set_promiscuous(struct
  761. return 0;
  762. }
  763. -static int dtsec_adjust_link(struct fman_mac *dtsec, u16 speed)
  764. -{
  765. - struct dtsec_regs __iomem *regs = dtsec->regs;
  766. - u32 tmp;
  767. -
  768. - if (!is_init_done(dtsec->dtsec_drv_param))
  769. - return -EINVAL;
  770. -
  771. - graceful_stop(dtsec);
  772. -
  773. - tmp = ioread32be(&regs->maccfg2);
  774. -
  775. - /* Full Duplex */
  776. - tmp |= MACCFG2_FULL_DUPLEX;
  777. -
  778. - tmp &= ~(MACCFG2_NIBBLE_MODE | MACCFG2_BYTE_MODE);
  779. - if (speed < SPEED_1000)
  780. - tmp |= MACCFG2_NIBBLE_MODE;
  781. - else if (speed == SPEED_1000)
  782. - tmp |= MACCFG2_BYTE_MODE;
  783. - iowrite32be(tmp, &regs->maccfg2);
  784. -
  785. - tmp = ioread32be(&regs->ecntrl);
  786. - if (speed == SPEED_100)
  787. - tmp |= DTSEC_ECNTRL_R100M;
  788. - else
  789. - tmp &= ~DTSEC_ECNTRL_R100M;
  790. - iowrite32be(tmp, &regs->ecntrl);
  791. -
  792. - graceful_start(dtsec);
  793. -
  794. - return 0;
  795. -}
  796. -
  797. -static int dtsec_restart_autoneg(struct fman_mac *dtsec)
  798. -{
  799. - u16 tmp_reg16;
  800. -
  801. - if (!is_init_done(dtsec->dtsec_drv_param))
  802. - return -EINVAL;
  803. -
  804. - tmp_reg16 = phy_read(dtsec->tbiphy, MII_BMCR);
  805. -
  806. - tmp_reg16 &= ~(BMCR_SPEED100 | BMCR_SPEED1000);
  807. - tmp_reg16 |= (BMCR_ANENABLE | BMCR_ANRESTART |
  808. - BMCR_FULLDPLX | BMCR_SPEED1000);
  809. -
  810. - phy_write(dtsec->tbiphy, MII_BMCR, tmp_reg16);
  811. -
  812. - return 0;
  813. -}
  814. -
  815. -static void adjust_link_dtsec(struct mac_device *mac_dev)
  816. -{
  817. - struct phy_device *phy_dev = mac_dev->phy_dev;
  818. - struct fman_mac *fman_mac;
  819. - bool rx_pause, tx_pause;
  820. - int err;
  821. -
  822. - fman_mac = mac_dev->fman_mac;
  823. - if (!phy_dev->link) {
  824. - dtsec_restart_autoneg(fman_mac);
  825. -
  826. - return;
  827. - }
  828. -
  829. - dtsec_adjust_link(fman_mac, phy_dev->speed);
  830. - mac_dev->update_speed(mac_dev, phy_dev->speed);
  831. - fman_get_pause_cfg(mac_dev, &rx_pause, &tx_pause);
  832. - err = fman_set_mac_active_pause(mac_dev, rx_pause, tx_pause);
  833. - if (err < 0)
  834. - dev_err(mac_dev->dev, "fman_set_mac_active_pause() = %d\n",
  835. - err);
  836. -}
  837. -
  838. static int dtsec_set_exception(struct fman_mac *dtsec,
  839. enum fman_mac_exceptions exception, bool enable)
  840. {
  841. struct dtsec_regs __iomem *regs = dtsec->regs;
  842. u32 bit_mask = 0;
  843. - if (!is_init_done(dtsec->dtsec_drv_param))
  844. - return -EINVAL;
  845. -
  846. if (exception != FM_MAC_EX_1G_1588_TS_RX_ERR) {
  847. bit_mask = get_exception_flag(exception);
  848. if (bit_mask) {
  849. @@ -1310,12 +1261,9 @@ static int dtsec_init(struct fman_mac *d
  850. {
  851. struct dtsec_regs __iomem *regs = dtsec->regs;
  852. struct dtsec_cfg *dtsec_drv_param;
  853. - u16 max_frm_ln;
  854. + u16 max_frm_ln, tbicon;
  855. int err;
  856. - if (is_init_done(dtsec->dtsec_drv_param))
  857. - return -EINVAL;
  858. -
  859. if (DEFAULT_RESET_ON_INIT &&
  860. (fman_reset_mac(dtsec->fm, dtsec->mac_id) != 0)) {
  861. pr_err("Can't reset MAC!\n");
  862. @@ -1330,38 +1278,19 @@ static int dtsec_init(struct fman_mac *d
  863. err = init(dtsec->regs, dtsec_drv_param, dtsec->phy_if,
  864. dtsec->max_speed, dtsec->addr, dtsec->exceptions,
  865. - dtsec->tbiphy->mdio.addr);
  866. + dtsec->tbidev->addr);
  867. if (err) {
  868. free_init_resources(dtsec);
  869. pr_err("DTSEC version doesn't support this i/f mode\n");
  870. return err;
  871. }
  872. - if (dtsec->phy_if == PHY_INTERFACE_MODE_SGMII) {
  873. - u16 tmp_reg16;
  874. -
  875. - /* Configure the TBI PHY Control Register */
  876. - tmp_reg16 = TBICON_CLK_SELECT | TBICON_SOFT_RESET;
  877. - phy_write(dtsec->tbiphy, MII_TBICON, tmp_reg16);
  878. -
  879. - tmp_reg16 = TBICON_CLK_SELECT;
  880. - phy_write(dtsec->tbiphy, MII_TBICON, tmp_reg16);
  881. -
  882. - tmp_reg16 = (BMCR_RESET | BMCR_ANENABLE |
  883. - BMCR_FULLDPLX | BMCR_SPEED1000);
  884. - phy_write(dtsec->tbiphy, MII_BMCR, tmp_reg16);
  885. -
  886. - if (dtsec->basex_if)
  887. - tmp_reg16 = TBIANA_1000X;
  888. - else
  889. - tmp_reg16 = TBIANA_SGMII;
  890. - phy_write(dtsec->tbiphy, MII_ADVERTISE, tmp_reg16);
  891. + /* Configure the TBI PHY Control Register */
  892. + tbicon = TBICON_CLK_SELECT | TBICON_SOFT_RESET;
  893. + mdiodev_write(dtsec->tbidev, MII_TBICON, tbicon);
  894. - tmp_reg16 = (BMCR_ANENABLE | BMCR_ANRESTART |
  895. - BMCR_FULLDPLX | BMCR_SPEED1000);
  896. -
  897. - phy_write(dtsec->tbiphy, MII_BMCR, tmp_reg16);
  898. - }
  899. + tbicon = TBICON_CLK_SELECT;
  900. + mdiodev_write(dtsec->tbidev, MII_TBICON, tbicon);
  901. /* Max Frame Length */
  902. max_frm_ln = (u16)ioread32be(&regs->maxfrm);
  903. @@ -1406,6 +1335,8 @@ static int dtsec_free(struct fman_mac *d
  904. kfree(dtsec->dtsec_drv_param);
  905. dtsec->dtsec_drv_param = NULL;
  906. + if (!IS_ERR_OR_NULL(dtsec->tbidev))
  907. + put_device(&dtsec->tbidev->dev);
  908. kfree(dtsec);
  909. return 0;
  910. @@ -1434,7 +1365,6 @@ static struct fman_mac *dtsec_config(str
  911. dtsec->regs = mac_dev->vaddr;
  912. dtsec->addr = ENET_ADDR_TO_UINT64(mac_dev->addr);
  913. - dtsec->max_speed = params->max_speed;
  914. dtsec->phy_if = mac_dev->phy_if;
  915. dtsec->mac_id = params->mac_id;
  916. dtsec->exceptions = (DTSEC_IMASK_BREN |
  917. @@ -1457,7 +1387,6 @@ static struct fman_mac *dtsec_config(str
  918. dtsec->en_tsu_err_exception = dtsec->dtsec_drv_param->ptp_exception_en;
  919. dtsec->fm = params->fm;
  920. - dtsec->basex_if = params->basex_if;
  921. /* Save FMan revision */
  922. fman_get_revision(dtsec->fm, &dtsec->fm_rev_info);
  923. @@ -1476,18 +1405,18 @@ int dtsec_initialization(struct mac_devi
  924. int err;
  925. struct fman_mac *dtsec;
  926. struct device_node *phy_node;
  927. + unsigned long capabilities;
  928. + unsigned long *supported;
  929. + mac_dev->phylink_ops = &dtsec_mac_ops;
  930. mac_dev->set_promisc = dtsec_set_promiscuous;
  931. mac_dev->change_addr = dtsec_modify_mac_address;
  932. mac_dev->add_hash_mac_addr = dtsec_add_hash_mac_address;
  933. mac_dev->remove_hash_mac_addr = dtsec_del_hash_mac_address;
  934. - mac_dev->set_tx_pause = dtsec_set_tx_pause_frames;
  935. - mac_dev->set_rx_pause = dtsec_accept_rx_pause_frames;
  936. mac_dev->set_exception = dtsec_set_exception;
  937. mac_dev->set_allmulti = dtsec_set_allmulti;
  938. mac_dev->set_tstamp = dtsec_set_tstamp;
  939. mac_dev->set_multi = fman_set_multi;
  940. - mac_dev->adjust_link = adjust_link_dtsec;
  941. mac_dev->enable = dtsec_enable;
  942. mac_dev->disable = dtsec_disable;
  943. @@ -1502,19 +1431,56 @@ int dtsec_initialization(struct mac_devi
  944. dtsec->dtsec_drv_param->tx_pad_crc = true;
  945. phy_node = of_parse_phandle(mac_node, "tbi-handle", 0);
  946. - if (!phy_node) {
  947. - pr_err("TBI PHY node is not available\n");
  948. + if (!phy_node || of_device_is_available(phy_node)) {
  949. + of_node_put(phy_node);
  950. err = -EINVAL;
  951. + dev_err_probe(mac_dev->dev, err,
  952. + "TBI PCS node is not available\n");
  953. goto _return_fm_mac_free;
  954. }
  955. - dtsec->tbiphy = of_phy_find_device(phy_node);
  956. - if (!dtsec->tbiphy) {
  957. - pr_err("of_phy_find_device (TBI PHY) failed\n");
  958. - err = -EINVAL;
  959. + dtsec->tbidev = of_mdio_find_device(phy_node);
  960. + of_node_put(phy_node);
  961. + if (!dtsec->tbidev) {
  962. + err = -EPROBE_DEFER;
  963. + dev_err_probe(mac_dev->dev, err,
  964. + "could not find mdiodev for PCS\n");
  965. goto _return_fm_mac_free;
  966. }
  967. - put_device(&dtsec->tbiphy->mdio.dev);
  968. + dtsec->pcs.ops = &dtsec_pcs_ops;
  969. + dtsec->pcs.poll = true;
  970. +
  971. + supported = mac_dev->phylink_config.supported_interfaces;
  972. +
  973. + /* FIXME: Can we use DTSEC_ID2_INT_FULL_OFF to determine if these are
  974. + * supported? If not, we can determine support via the phy if SerDes
  975. + * support is added.
  976. + */
  977. + if (mac_dev->phy_if == PHY_INTERFACE_MODE_SGMII ||
  978. + mac_dev->phy_if == PHY_INTERFACE_MODE_1000BASEX) {
  979. + __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
  980. + __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
  981. + } else if (mac_dev->phy_if == PHY_INTERFACE_MODE_2500BASEX) {
  982. + __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
  983. + }
  984. +
  985. + if (!(ioread32be(&dtsec->regs->tsec_id2) & DTSEC_ID2_INT_REDUCED_OFF)) {
  986. + phy_interface_set_rgmii(supported);
  987. +
  988. + /* DTSEC_ID2_INT_REDUCED_OFF indicates that the dTSEC supports
  989. + * RMII and RGMII. However, the only SoCs which support RMII
  990. + * are the P1017 and P1023. Avoid advertising this mode on
  991. + * other SoCs. This is a bit of a moot point, since there's no
  992. + * in-tree support for ethernet on these platforms...
  993. + */
  994. + if (of_machine_is_compatible("fsl,P1023") ||
  995. + of_machine_is_compatible("fsl,P1023RDB"))
  996. + __set_bit(PHY_INTERFACE_MODE_RMII, supported);
  997. + }
  998. +
  999. + capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
  1000. + capabilities |= MAC_10 | MAC_100 | MAC_1000FD | MAC_2500FD;
  1001. + mac_dev->phylink_config.mac_capabilities = capabilities;
  1002. err = dtsec_init(dtsec);
  1003. if (err < 0)
  1004. --- a/drivers/net/ethernet/freescale/fman/fman_mac.h
  1005. +++ b/drivers/net/ethernet/freescale/fman/fman_mac.h
  1006. @@ -170,20 +170,10 @@ struct fman_mac_params {
  1007. * 0 - FM_MAX_NUM_OF_10G_MACS
  1008. */
  1009. u8 mac_id;
  1010. - /* Note that the speed should indicate the maximum rate that
  1011. - * this MAC should support rather than the actual speed;
  1012. - */
  1013. - u16 max_speed;
  1014. /* A handle to the FM object this port related to */
  1015. void *fm;
  1016. fman_mac_exception_cb *event_cb; /* MDIO Events Callback Routine */
  1017. fman_mac_exception_cb *exception_cb;/* Exception Callback Routine */
  1018. - /* SGMII/QSGII interface with 1000BaseX auto-negotiation between MAC
  1019. - * and phy or backplane; Note: 1000BaseX auto-negotiation relates only
  1020. - * to interface between MAC and phy/backplane, SGMII phy can still
  1021. - * synchronize with far-end phy at 10Mbps, 100Mbps or 1000Mbps
  1022. - */
  1023. - bool basex_if;
  1024. };
  1025. struct eth_hash_t {
  1026. --- a/drivers/net/ethernet/freescale/fman/fman_memac.c
  1027. +++ b/drivers/net/ethernet/freescale/fman/fman_memac.c
  1028. @@ -278,9 +278,6 @@ struct fman_mac {
  1029. struct memac_regs __iomem *regs;
  1030. /* MAC address of device */
  1031. u64 addr;
  1032. - /* Ethernet physical interface */
  1033. - phy_interface_t phy_if;
  1034. - u16 max_speed;
  1035. struct mac_device *dev_id; /* device cookie used by the exception cbs */
  1036. fman_mac_exception_cb *exception_cb;
  1037. fman_mac_exception_cb *event_cb;
  1038. @@ -293,12 +290,12 @@ struct fman_mac {
  1039. struct memac_cfg *memac_drv_param;
  1040. void *fm;
  1041. struct fman_rev_info fm_rev_info;
  1042. - bool basex_if;
  1043. struct phy *serdes;
  1044. struct phylink_pcs *sgmii_pcs;
  1045. struct phylink_pcs *qsgmii_pcs;
  1046. struct phylink_pcs *xfi_pcs;
  1047. bool allmulti_enabled;
  1048. + bool rgmii_no_half_duplex;
  1049. };
  1050. static void add_addr_in_paddr(struct memac_regs __iomem *regs, const u8 *adr,
  1051. @@ -356,7 +353,6 @@ static void set_exception(struct memac_r
  1052. }
  1053. static int init(struct memac_regs __iomem *regs, struct memac_cfg *cfg,
  1054. - phy_interface_t phy_if, u16 speed, bool slow_10g_if,
  1055. u32 exceptions)
  1056. {
  1057. u32 tmp;
  1058. @@ -384,41 +380,6 @@ static int init(struct memac_regs __iome
  1059. iowrite32be((u32)cfg->pause_quanta, &regs->pause_quanta[0]);
  1060. iowrite32be((u32)0, &regs->pause_thresh[0]);
  1061. - /* IF_MODE */
  1062. - tmp = 0;
  1063. - switch (phy_if) {
  1064. - case PHY_INTERFACE_MODE_XGMII:
  1065. - tmp |= IF_MODE_10G;
  1066. - break;
  1067. - case PHY_INTERFACE_MODE_MII:
  1068. - tmp |= IF_MODE_MII;
  1069. - break;
  1070. - default:
  1071. - tmp |= IF_MODE_GMII;
  1072. - if (phy_if == PHY_INTERFACE_MODE_RGMII ||
  1073. - phy_if == PHY_INTERFACE_MODE_RGMII_ID ||
  1074. - phy_if == PHY_INTERFACE_MODE_RGMII_RXID ||
  1075. - phy_if == PHY_INTERFACE_MODE_RGMII_TXID)
  1076. - tmp |= IF_MODE_RGMII | IF_MODE_RGMII_AUTO;
  1077. - }
  1078. - iowrite32be(tmp, &regs->if_mode);
  1079. -
  1080. - /* TX_FIFO_SECTIONS */
  1081. - tmp = 0;
  1082. - if (phy_if == PHY_INTERFACE_MODE_XGMII) {
  1083. - if (slow_10g_if) {
  1084. - tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G |
  1085. - TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G);
  1086. - } else {
  1087. - tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_10G |
  1088. - TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G);
  1089. - }
  1090. - } else {
  1091. - tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_1G |
  1092. - TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G);
  1093. - }
  1094. - iowrite32be(tmp, &regs->tx_fifo_sections);
  1095. -
  1096. /* clear all pending events and set-up interrupts */
  1097. iowrite32be(0xffffffff, &regs->ievent);
  1098. set_exception(regs, exceptions, true);
  1099. @@ -458,24 +419,6 @@ static u32 get_mac_addr_hash_code(u64 et
  1100. return xor_val;
  1101. }
  1102. -static void setup_sgmii_internal(struct fman_mac *memac,
  1103. - struct phylink_pcs *pcs,
  1104. - struct fixed_phy_status *fixed_link)
  1105. -{
  1106. - __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
  1107. - phy_interface_t iface = memac->basex_if ? PHY_INTERFACE_MODE_1000BASEX :
  1108. - PHY_INTERFACE_MODE_SGMII;
  1109. - unsigned int mode = fixed_link ? MLO_AN_FIXED : MLO_AN_INBAND;
  1110. -
  1111. - linkmode_set_pause(advertising, true, true);
  1112. - pcs->ops->pcs_config(pcs, mode, iface, advertising, true);
  1113. - if (fixed_link)
  1114. - pcs->ops->pcs_link_up(pcs, mode, iface, fixed_link->speed,
  1115. - fixed_link->duplex);
  1116. - else
  1117. - pcs->ops->pcs_an_restart(pcs);
  1118. -}
  1119. -
  1120. static int check_init_parameters(struct fman_mac *memac)
  1121. {
  1122. if (!memac->exception_cb) {
  1123. @@ -581,41 +524,31 @@ static void free_init_resources(struct f
  1124. memac->unicast_addr_hash = NULL;
  1125. }
  1126. -static bool is_init_done(struct memac_cfg *memac_drv_params)
  1127. -{
  1128. - /* Checks if mEMAC driver parameters were initialized */
  1129. - if (!memac_drv_params)
  1130. - return true;
  1131. -
  1132. - return false;
  1133. -}
  1134. -
  1135. static int memac_enable(struct fman_mac *memac)
  1136. {
  1137. - struct memac_regs __iomem *regs = memac->regs;
  1138. - u32 tmp;
  1139. + int ret;
  1140. - if (!is_init_done(memac->memac_drv_param))
  1141. - return -EINVAL;
  1142. + ret = phy_init(memac->serdes);
  1143. + if (ret) {
  1144. + dev_err(memac->dev_id->dev,
  1145. + "could not initialize serdes: %pe\n", ERR_PTR(ret));
  1146. + return ret;
  1147. + }
  1148. - tmp = ioread32be(&regs->command_config);
  1149. - tmp |= CMD_CFG_RX_EN | CMD_CFG_TX_EN;
  1150. - iowrite32be(tmp, &regs->command_config);
  1151. + ret = phy_power_on(memac->serdes);
  1152. + if (ret) {
  1153. + dev_err(memac->dev_id->dev,
  1154. + "could not power on serdes: %pe\n", ERR_PTR(ret));
  1155. + phy_exit(memac->serdes);
  1156. + }
  1157. - return 0;
  1158. + return ret;
  1159. }
  1160. static void memac_disable(struct fman_mac *memac)
  1161. -
  1162. {
  1163. - struct memac_regs __iomem *regs = memac->regs;
  1164. - u32 tmp;
  1165. -
  1166. - WARN_ON_ONCE(!is_init_done(memac->memac_drv_param));
  1167. -
  1168. - tmp = ioread32be(&regs->command_config);
  1169. - tmp &= ~(CMD_CFG_RX_EN | CMD_CFG_TX_EN);
  1170. - iowrite32be(tmp, &regs->command_config);
  1171. + phy_power_off(memac->serdes);
  1172. + phy_exit(memac->serdes);
  1173. }
  1174. static int memac_set_promiscuous(struct fman_mac *memac, bool new_val)
  1175. @@ -623,9 +556,6 @@ static int memac_set_promiscuous(struct
  1176. struct memac_regs __iomem *regs = memac->regs;
  1177. u32 tmp;
  1178. - if (!is_init_done(memac->memac_drv_param))
  1179. - return -EINVAL;
  1180. -
  1181. tmp = ioread32be(&regs->command_config);
  1182. if (new_val)
  1183. tmp |= CMD_CFG_PROMIS_EN;
  1184. @@ -637,73 +567,12 @@ static int memac_set_promiscuous(struct
  1185. return 0;
  1186. }
  1187. -static int memac_adjust_link(struct fman_mac *memac, u16 speed)
  1188. -{
  1189. - struct memac_regs __iomem *regs = memac->regs;
  1190. - u32 tmp;
  1191. -
  1192. - if (!is_init_done(memac->memac_drv_param))
  1193. - return -EINVAL;
  1194. -
  1195. - tmp = ioread32be(&regs->if_mode);
  1196. -
  1197. - /* Set full duplex */
  1198. - tmp &= ~IF_MODE_HD;
  1199. -
  1200. - if (phy_interface_mode_is_rgmii(memac->phy_if)) {
  1201. - /* Configure RGMII in manual mode */
  1202. - tmp &= ~IF_MODE_RGMII_AUTO;
  1203. - tmp &= ~IF_MODE_RGMII_SP_MASK;
  1204. - /* Full duplex */
  1205. - tmp |= IF_MODE_RGMII_FD;
  1206. -
  1207. - switch (speed) {
  1208. - case SPEED_1000:
  1209. - tmp |= IF_MODE_RGMII_1000;
  1210. - break;
  1211. - case SPEED_100:
  1212. - tmp |= IF_MODE_RGMII_100;
  1213. - break;
  1214. - case SPEED_10:
  1215. - tmp |= IF_MODE_RGMII_10;
  1216. - break;
  1217. - default:
  1218. - break;
  1219. - }
  1220. - }
  1221. -
  1222. - iowrite32be(tmp, &regs->if_mode);
  1223. -
  1224. - return 0;
  1225. -}
  1226. -
  1227. -static void adjust_link_memac(struct mac_device *mac_dev)
  1228. -{
  1229. - struct phy_device *phy_dev = mac_dev->phy_dev;
  1230. - struct fman_mac *fman_mac;
  1231. - bool rx_pause, tx_pause;
  1232. - int err;
  1233. -
  1234. - fman_mac = mac_dev->fman_mac;
  1235. - memac_adjust_link(fman_mac, phy_dev->speed);
  1236. - mac_dev->update_speed(mac_dev, phy_dev->speed);
  1237. -
  1238. - fman_get_pause_cfg(mac_dev, &rx_pause, &tx_pause);
  1239. - err = fman_set_mac_active_pause(mac_dev, rx_pause, tx_pause);
  1240. - if (err < 0)
  1241. - dev_err(mac_dev->dev, "fman_set_mac_active_pause() = %d\n",
  1242. - err);
  1243. -}
  1244. -
  1245. static int memac_set_tx_pause_frames(struct fman_mac *memac, u8 priority,
  1246. u16 pause_time, u16 thresh_time)
  1247. {
  1248. struct memac_regs __iomem *regs = memac->regs;
  1249. u32 tmp;
  1250. - if (!is_init_done(memac->memac_drv_param))
  1251. - return -EINVAL;
  1252. -
  1253. tmp = ioread32be(&regs->tx_fifo_sections);
  1254. GET_TX_EMPTY_DEFAULT_VALUE(tmp);
  1255. @@ -738,9 +607,6 @@ static int memac_accept_rx_pause_frames(
  1256. struct memac_regs __iomem *regs = memac->regs;
  1257. u32 tmp;
  1258. - if (!is_init_done(memac->memac_drv_param))
  1259. - return -EINVAL;
  1260. -
  1261. tmp = ioread32be(&regs->command_config);
  1262. if (en)
  1263. tmp &= ~CMD_CFG_PAUSE_IGNORE;
  1264. @@ -752,12 +618,175 @@ static int memac_accept_rx_pause_frames(
  1265. return 0;
  1266. }
  1267. +static void memac_validate(struct phylink_config *config,
  1268. + unsigned long *supported,
  1269. + struct phylink_link_state *state)
  1270. +{
  1271. + struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
  1272. + unsigned long caps = config->mac_capabilities;
  1273. +
  1274. + if (phy_interface_mode_is_rgmii(state->interface) &&
  1275. + memac->rgmii_no_half_duplex)
  1276. + caps &= ~(MAC_10HD | MAC_100HD);
  1277. +
  1278. + phylink_validate_mask_caps(supported, state, caps);
  1279. +}
  1280. +
  1281. +/**
  1282. + * memac_if_mode() - Convert an interface mode into an IF_MODE config
  1283. + * @interface: A phy interface mode
  1284. + *
  1285. + * Return: A configuration word, suitable for programming into the lower bits
  1286. + * of %IF_MODE.
  1287. + */
  1288. +static u32 memac_if_mode(phy_interface_t interface)
  1289. +{
  1290. + switch (interface) {
  1291. + case PHY_INTERFACE_MODE_MII:
  1292. + return IF_MODE_MII;
  1293. + case PHY_INTERFACE_MODE_RGMII:
  1294. + case PHY_INTERFACE_MODE_RGMII_ID:
  1295. + case PHY_INTERFACE_MODE_RGMII_RXID:
  1296. + case PHY_INTERFACE_MODE_RGMII_TXID:
  1297. + return IF_MODE_GMII | IF_MODE_RGMII;
  1298. + case PHY_INTERFACE_MODE_SGMII:
  1299. + case PHY_INTERFACE_MODE_1000BASEX:
  1300. + case PHY_INTERFACE_MODE_QSGMII:
  1301. + return IF_MODE_GMII;
  1302. + case PHY_INTERFACE_MODE_10GBASER:
  1303. + return IF_MODE_10G;
  1304. + default:
  1305. + WARN_ON_ONCE(1);
  1306. + return 0;
  1307. + }
  1308. +}
  1309. +
  1310. +static struct phylink_pcs *memac_select_pcs(struct phylink_config *config,
  1311. + phy_interface_t iface)
  1312. +{
  1313. + struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
  1314. +
  1315. + switch (iface) {
  1316. + case PHY_INTERFACE_MODE_SGMII:
  1317. + case PHY_INTERFACE_MODE_1000BASEX:
  1318. + return memac->sgmii_pcs;
  1319. + case PHY_INTERFACE_MODE_QSGMII:
  1320. + return memac->qsgmii_pcs;
  1321. + case PHY_INTERFACE_MODE_10GBASER:
  1322. + return memac->xfi_pcs;
  1323. + default:
  1324. + return NULL;
  1325. + }
  1326. +}
  1327. +
  1328. +static int memac_prepare(struct phylink_config *config, unsigned int mode,
  1329. + phy_interface_t iface)
  1330. +{
  1331. + struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
  1332. +
  1333. + switch (iface) {
  1334. + case PHY_INTERFACE_MODE_SGMII:
  1335. + case PHY_INTERFACE_MODE_1000BASEX:
  1336. + case PHY_INTERFACE_MODE_QSGMII:
  1337. + case PHY_INTERFACE_MODE_10GBASER:
  1338. + return phy_set_mode_ext(memac->serdes, PHY_MODE_ETHERNET,
  1339. + iface);
  1340. + default:
  1341. + return 0;
  1342. + }
  1343. +}
  1344. +
  1345. +static void memac_mac_config(struct phylink_config *config, unsigned int mode,
  1346. + const struct phylink_link_state *state)
  1347. +{
  1348. + struct mac_device *mac_dev = fman_config_to_mac(config);
  1349. + struct memac_regs __iomem *regs = mac_dev->fman_mac->regs;
  1350. + u32 tmp = ioread32be(&regs->if_mode);
  1351. +
  1352. + tmp &= ~(IF_MODE_MASK | IF_MODE_RGMII);
  1353. + tmp |= memac_if_mode(state->interface);
  1354. + if (phylink_autoneg_inband(mode))
  1355. + tmp |= IF_MODE_RGMII_AUTO;
  1356. + iowrite32be(tmp, &regs->if_mode);
  1357. +}
  1358. +
  1359. +static void memac_link_up(struct phylink_config *config, struct phy_device *phy,
  1360. + unsigned int mode, phy_interface_t interface,
  1361. + int speed, int duplex, bool tx_pause, bool rx_pause)
  1362. +{
  1363. + struct mac_device *mac_dev = fman_config_to_mac(config);
  1364. + struct fman_mac *memac = mac_dev->fman_mac;
  1365. + struct memac_regs __iomem *regs = memac->regs;
  1366. + u32 tmp = memac_if_mode(interface);
  1367. + u16 pause_time = tx_pause ? FSL_FM_PAUSE_TIME_ENABLE :
  1368. + FSL_FM_PAUSE_TIME_DISABLE;
  1369. +
  1370. + memac_set_tx_pause_frames(memac, 0, pause_time, 0);
  1371. + memac_accept_rx_pause_frames(memac, rx_pause);
  1372. +
  1373. + if (duplex == DUPLEX_HALF)
  1374. + tmp |= IF_MODE_HD;
  1375. +
  1376. + switch (speed) {
  1377. + case SPEED_1000:
  1378. + tmp |= IF_MODE_RGMII_1000;
  1379. + break;
  1380. + case SPEED_100:
  1381. + tmp |= IF_MODE_RGMII_100;
  1382. + break;
  1383. + case SPEED_10:
  1384. + tmp |= IF_MODE_RGMII_10;
  1385. + break;
  1386. + }
  1387. + iowrite32be(tmp, &regs->if_mode);
  1388. +
  1389. + /* TODO: EEE? */
  1390. +
  1391. + if (speed == SPEED_10000) {
  1392. + if (memac->fm_rev_info.major == 6 &&
  1393. + memac->fm_rev_info.minor == 4)
  1394. + tmp = TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G;
  1395. + else
  1396. + tmp = TX_FIFO_SECTIONS_TX_AVAIL_10G;
  1397. + tmp |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G;
  1398. + } else {
  1399. + tmp = TX_FIFO_SECTIONS_TX_AVAIL_1G |
  1400. + TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G;
  1401. + }
  1402. + iowrite32be(tmp, &regs->tx_fifo_sections);
  1403. +
  1404. + mac_dev->update_speed(mac_dev, speed);
  1405. +
  1406. + tmp = ioread32be(&regs->command_config);
  1407. + tmp |= CMD_CFG_RX_EN | CMD_CFG_TX_EN;
  1408. + iowrite32be(tmp, &regs->command_config);
  1409. +}
  1410. +
  1411. +static void memac_link_down(struct phylink_config *config, unsigned int mode,
  1412. + phy_interface_t interface)
  1413. +{
  1414. + struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
  1415. + struct memac_regs __iomem *regs = memac->regs;
  1416. + u32 tmp;
  1417. +
  1418. + /* TODO: graceful */
  1419. + tmp = ioread32be(&regs->command_config);
  1420. + tmp &= ~(CMD_CFG_RX_EN | CMD_CFG_TX_EN);
  1421. + iowrite32be(tmp, &regs->command_config);
  1422. +}
  1423. +
  1424. +static const struct phylink_mac_ops memac_mac_ops = {
  1425. + .validate = memac_validate,
  1426. + .mac_select_pcs = memac_select_pcs,
  1427. + .mac_prepare = memac_prepare,
  1428. + .mac_config = memac_mac_config,
  1429. + .mac_link_up = memac_link_up,
  1430. + .mac_link_down = memac_link_down,
  1431. +};
  1432. +
  1433. static int memac_modify_mac_address(struct fman_mac *memac,
  1434. const enet_addr_t *enet_addr)
  1435. {
  1436. - if (!is_init_done(memac->memac_drv_param))
  1437. - return -EINVAL;
  1438. -
  1439. add_addr_in_paddr(memac->regs, (const u8 *)(*enet_addr), 0);
  1440. return 0;
  1441. @@ -771,9 +800,6 @@ static int memac_add_hash_mac_address(st
  1442. u32 hash;
  1443. u64 addr;
  1444. - if (!is_init_done(memac->memac_drv_param))
  1445. - return -EINVAL;
  1446. -
  1447. addr = ENET_ADDR_TO_UINT64(*eth_addr);
  1448. if (!(addr & GROUP_ADDRESS)) {
  1449. @@ -802,9 +828,6 @@ static int memac_set_allmulti(struct fma
  1450. u32 entry;
  1451. struct memac_regs __iomem *regs = memac->regs;
  1452. - if (!is_init_done(memac->memac_drv_param))
  1453. - return -EINVAL;
  1454. -
  1455. if (enable) {
  1456. for (entry = 0; entry < HASH_TABLE_SIZE; entry++)
  1457. iowrite32be(entry | HASH_CTRL_MCAST_EN,
  1458. @@ -834,9 +857,6 @@ static int memac_del_hash_mac_address(st
  1459. u32 hash;
  1460. u64 addr;
  1461. - if (!is_init_done(memac->memac_drv_param))
  1462. - return -EINVAL;
  1463. -
  1464. addr = ENET_ADDR_TO_UINT64(*eth_addr);
  1465. hash = get_mac_addr_hash_code(addr) & HASH_CTRL_ADDR_MASK;
  1466. @@ -864,9 +884,6 @@ static int memac_set_exception(struct fm
  1467. {
  1468. u32 bit_mask = 0;
  1469. - if (!is_init_done(memac->memac_drv_param))
  1470. - return -EINVAL;
  1471. -
  1472. bit_mask = get_exception_flag(exception);
  1473. if (bit_mask) {
  1474. if (enable)
  1475. @@ -886,23 +903,15 @@ static int memac_init(struct fman_mac *m
  1476. {
  1477. struct memac_cfg *memac_drv_param;
  1478. enet_addr_t eth_addr;
  1479. - bool slow_10g_if = false;
  1480. - struct fixed_phy_status *fixed_link = NULL;
  1481. int err;
  1482. u32 reg32 = 0;
  1483. - if (is_init_done(memac->memac_drv_param))
  1484. - return -EINVAL;
  1485. -
  1486. err = check_init_parameters(memac);
  1487. if (err)
  1488. return err;
  1489. memac_drv_param = memac->memac_drv_param;
  1490. - if (memac->fm_rev_info.major == 6 && memac->fm_rev_info.minor == 4)
  1491. - slow_10g_if = true;
  1492. -
  1493. /* First, reset the MAC if desired. */
  1494. if (memac_drv_param->reset_on_init) {
  1495. err = reset(memac->regs);
  1496. @@ -918,10 +927,7 @@ static int memac_init(struct fman_mac *m
  1497. add_addr_in_paddr(memac->regs, (const u8 *)eth_addr, 0);
  1498. }
  1499. - fixed_link = memac_drv_param->fixed_link;
  1500. -
  1501. - init(memac->regs, memac->memac_drv_param, memac->phy_if,
  1502. - memac->max_speed, slow_10g_if, memac->exceptions);
  1503. + init(memac->regs, memac->memac_drv_param, memac->exceptions);
  1504. /* FM_RX_FIFO_CORRUPT_ERRATA_10GMAC_A006320 errata workaround
  1505. * Exists only in FMan 6.0 and 6.3.
  1506. @@ -937,11 +943,6 @@ static int memac_init(struct fman_mac *m
  1507. iowrite32be(reg32, &memac->regs->command_config);
  1508. }
  1509. - if (memac->phy_if == PHY_INTERFACE_MODE_SGMII)
  1510. - setup_sgmii_internal(memac, memac->sgmii_pcs, fixed_link);
  1511. - else if (memac->phy_if == PHY_INTERFACE_MODE_QSGMII)
  1512. - setup_sgmii_internal(memac, memac->qsgmii_pcs, fixed_link);
  1513. -
  1514. /* Max Frame Length */
  1515. err = fman_set_mac_max_frame(memac->fm, memac->mac_id,
  1516. memac_drv_param->max_frame_length);
  1517. @@ -970,9 +971,6 @@ static int memac_init(struct fman_mac *m
  1518. fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,
  1519. FMAN_INTR_TYPE_NORMAL, memac_exception, memac);
  1520. - kfree(memac_drv_param);
  1521. - memac->memac_drv_param = NULL;
  1522. -
  1523. return 0;
  1524. }
  1525. @@ -995,7 +993,6 @@ static int memac_free(struct fman_mac *m
  1526. pcs_put(memac->sgmii_pcs);
  1527. pcs_put(memac->qsgmii_pcs);
  1528. pcs_put(memac->xfi_pcs);
  1529. -
  1530. kfree(memac->memac_drv_param);
  1531. kfree(memac);
  1532. @@ -1028,8 +1025,6 @@ static struct fman_mac *memac_config(str
  1533. memac->addr = ENET_ADDR_TO_UINT64(mac_dev->addr);
  1534. memac->regs = mac_dev->vaddr;
  1535. - memac->max_speed = params->max_speed;
  1536. - memac->phy_if = mac_dev->phy_if;
  1537. memac->mac_id = params->mac_id;
  1538. memac->exceptions = (MEMAC_IMASK_TSECC_ER | MEMAC_IMASK_TECC_ER |
  1539. MEMAC_IMASK_RECC_ER | MEMAC_IMASK_MGI);
  1540. @@ -1037,7 +1032,6 @@ static struct fman_mac *memac_config(str
  1541. memac->event_cb = params->event_cb;
  1542. memac->dev_id = mac_dev;
  1543. memac->fm = params->fm;
  1544. - memac->basex_if = params->basex_if;
  1545. /* Save FMan revision */
  1546. fman_get_revision(memac->fm, &memac->fm_rev_info);
  1547. @@ -1064,37 +1058,44 @@ static struct phylink_pcs *memac_pcs_cre
  1548. return pcs;
  1549. }
  1550. +static bool memac_supports(struct mac_device *mac_dev, phy_interface_t iface)
  1551. +{
  1552. + /* If there's no serdes device, assume that it's been configured for
  1553. + * whatever the default interface mode is.
  1554. + */
  1555. + if (!mac_dev->fman_mac->serdes)
  1556. + return mac_dev->phy_if == iface;
  1557. + /* Otherwise, ask the serdes */
  1558. + return !phy_validate(mac_dev->fman_mac->serdes, PHY_MODE_ETHERNET,
  1559. + iface, NULL);
  1560. +}
  1561. +
  1562. int memac_initialization(struct mac_device *mac_dev,
  1563. struct device_node *mac_node,
  1564. struct fman_mac_params *params)
  1565. {
  1566. int err;
  1567. + struct device_node *fixed;
  1568. struct phylink_pcs *pcs;
  1569. - struct fixed_phy_status *fixed_link;
  1570. struct fman_mac *memac;
  1571. + unsigned long capabilities;
  1572. + unsigned long *supported;
  1573. + mac_dev->phylink_ops = &memac_mac_ops;
  1574. mac_dev->set_promisc = memac_set_promiscuous;
  1575. mac_dev->change_addr = memac_modify_mac_address;
  1576. mac_dev->add_hash_mac_addr = memac_add_hash_mac_address;
  1577. mac_dev->remove_hash_mac_addr = memac_del_hash_mac_address;
  1578. - mac_dev->set_tx_pause = memac_set_tx_pause_frames;
  1579. - mac_dev->set_rx_pause = memac_accept_rx_pause_frames;
  1580. mac_dev->set_exception = memac_set_exception;
  1581. mac_dev->set_allmulti = memac_set_allmulti;
  1582. mac_dev->set_tstamp = memac_set_tstamp;
  1583. mac_dev->set_multi = fman_set_multi;
  1584. - mac_dev->adjust_link = adjust_link_memac;
  1585. mac_dev->enable = memac_enable;
  1586. mac_dev->disable = memac_disable;
  1587. - if (params->max_speed == SPEED_10000)
  1588. - mac_dev->phy_if = PHY_INTERFACE_MODE_XGMII;
  1589. -
  1590. mac_dev->fman_mac = memac_config(mac_dev, params);
  1591. - if (!mac_dev->fman_mac) {
  1592. - err = -EINVAL;
  1593. - goto _return;
  1594. - }
  1595. + if (!mac_dev->fman_mac)
  1596. + return -EINVAL;
  1597. memac = mac_dev->fman_mac;
  1598. memac->memac_drv_param->max_frame_length = fman_get_max_frm();
  1599. @@ -1136,9 +1137,9 @@ int memac_initialization(struct mac_devi
  1600. else
  1601. pcs = memac_pcs_create(mac_node, err);
  1602. - if (!pcs) {
  1603. - dev_err(mac_dev->dev, "missing pcs\n");
  1604. - err = -ENOENT;
  1605. + if (IS_ERR(pcs)) {
  1606. + err = PTR_ERR(pcs);
  1607. + dev_err_probe(mac_dev->dev, err, "missing pcs\n");
  1608. goto _return_fm_mac_free;
  1609. }
  1610. @@ -1159,84 +1160,100 @@ int memac_initialization(struct mac_devi
  1611. } else if (IS_ERR(memac->serdes)) {
  1612. dev_err_probe(mac_dev->dev, err, "could not get serdes\n");
  1613. goto _return_fm_mac_free;
  1614. - } else {
  1615. - err = phy_init(memac->serdes);
  1616. - if (err) {
  1617. - dev_err_probe(mac_dev->dev, err,
  1618. - "could not initialize serdes\n");
  1619. - goto _return_fm_mac_free;
  1620. - }
  1621. -
  1622. - err = phy_power_on(memac->serdes);
  1623. - if (err) {
  1624. - dev_err_probe(mac_dev->dev, err,
  1625. - "could not power on serdes\n");
  1626. - goto _return_phy_exit;
  1627. - }
  1628. -
  1629. - if (memac->phy_if == PHY_INTERFACE_MODE_SGMII ||
  1630. - memac->phy_if == PHY_INTERFACE_MODE_1000BASEX ||
  1631. - memac->phy_if == PHY_INTERFACE_MODE_2500BASEX ||
  1632. - memac->phy_if == PHY_INTERFACE_MODE_QSGMII ||
  1633. - memac->phy_if == PHY_INTERFACE_MODE_XGMII) {
  1634. - err = phy_set_mode_ext(memac->serdes, PHY_MODE_ETHERNET,
  1635. - memac->phy_if);
  1636. - if (err) {
  1637. - dev_err_probe(mac_dev->dev, err,
  1638. - "could not set serdes mode to %s\n",
  1639. - phy_modes(memac->phy_if));
  1640. - goto _return_phy_power_off;
  1641. - }
  1642. - }
  1643. }
  1644. - if (!mac_dev->phy_node && of_phy_is_fixed_link(mac_node)) {
  1645. - struct phy_device *phy;
  1646. -
  1647. - err = of_phy_register_fixed_link(mac_node);
  1648. - if (err)
  1649. - goto _return_phy_power_off;
  1650. -
  1651. - fixed_link = kzalloc(sizeof(*fixed_link), GFP_KERNEL);
  1652. - if (!fixed_link) {
  1653. - err = -ENOMEM;
  1654. - goto _return_phy_power_off;
  1655. - }
  1656. + /* The internal connection to the serdes is XGMII, but this isn't
  1657. + * really correct for the phy mode (which is the external connection).
  1658. + * However, this is how all older device trees say that they want
  1659. + * 10GBASE-R (aka XFI), so just convert it for them.
  1660. + */
  1661. + if (mac_dev->phy_if == PHY_INTERFACE_MODE_XGMII)
  1662. + mac_dev->phy_if = PHY_INTERFACE_MODE_10GBASER;
  1663. - mac_dev->phy_node = of_node_get(mac_node);
  1664. - phy = of_phy_find_device(mac_dev->phy_node);
  1665. - if (!phy) {
  1666. - err = -EINVAL;
  1667. - of_node_put(mac_dev->phy_node);
  1668. - goto _return_fixed_link_free;
  1669. - }
  1670. + /* TODO: The following interface modes are supported by (some) hardware
  1671. + * but not by this driver:
  1672. + * - 1000BASE-KX
  1673. + * - 10GBASE-KR
  1674. + * - XAUI/HiGig
  1675. + */
  1676. + supported = mac_dev->phylink_config.supported_interfaces;
  1677. - fixed_link->link = phy->link;
  1678. - fixed_link->speed = phy->speed;
  1679. - fixed_link->duplex = phy->duplex;
  1680. - fixed_link->pause = phy->pause;
  1681. - fixed_link->asym_pause = phy->asym_pause;
  1682. + /* Note that half duplex is only supported on 10/100M interfaces. */
  1683. - put_device(&phy->mdio.dev);
  1684. - memac->memac_drv_param->fixed_link = fixed_link;
  1685. + if (memac->sgmii_pcs &&
  1686. + (memac_supports(mac_dev, PHY_INTERFACE_MODE_SGMII) ||
  1687. + memac_supports(mac_dev, PHY_INTERFACE_MODE_1000BASEX))) {
  1688. + __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
  1689. + __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
  1690. + }
  1691. +
  1692. + if (memac->sgmii_pcs &&
  1693. + memac_supports(mac_dev, PHY_INTERFACE_MODE_2500BASEX))
  1694. + __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
  1695. +
  1696. + if (memac->qsgmii_pcs &&
  1697. + memac_supports(mac_dev, PHY_INTERFACE_MODE_QSGMII))
  1698. + __set_bit(PHY_INTERFACE_MODE_QSGMII, supported);
  1699. + else if (mac_dev->phy_if == PHY_INTERFACE_MODE_QSGMII)
  1700. + dev_warn(mac_dev->dev, "no QSGMII pcs specified\n");
  1701. +
  1702. + if (memac->xfi_pcs &&
  1703. + memac_supports(mac_dev, PHY_INTERFACE_MODE_10GBASER)) {
  1704. + __set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
  1705. + } else {
  1706. + /* From what I can tell, no 10g macs support RGMII. */
  1707. + phy_interface_set_rgmii(supported);
  1708. + __set_bit(PHY_INTERFACE_MODE_MII, supported);
  1709. }
  1710. + capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE | MAC_10 | MAC_100;
  1711. + capabilities |= MAC_1000FD | MAC_2500FD | MAC_10000FD;
  1712. +
  1713. + /* These SoCs don't support half duplex at all; there's no different
  1714. + * FMan version or compatible, so we just have to check the machine
  1715. + * compatible instead
  1716. + */
  1717. + if (of_machine_is_compatible("fsl,ls1043a") ||
  1718. + of_machine_is_compatible("fsl,ls1046a") ||
  1719. + of_machine_is_compatible("fsl,B4QDS"))
  1720. + capabilities &= ~(MAC_10HD | MAC_100HD);
  1721. +
  1722. + mac_dev->phylink_config.mac_capabilities = capabilities;
  1723. +
  1724. + /* The T2080 and T4240 don't support half duplex RGMII. There is no
  1725. + * other way to identify these SoCs, so just use the machine
  1726. + * compatible.
  1727. + */
  1728. + if (of_machine_is_compatible("fsl,T2080QDS") ||
  1729. + of_machine_is_compatible("fsl,T2080RDB") ||
  1730. + of_machine_is_compatible("fsl,T2081QDS") ||
  1731. + of_machine_is_compatible("fsl,T4240QDS") ||
  1732. + of_machine_is_compatible("fsl,T4240RDB"))
  1733. + memac->rgmii_no_half_duplex = true;
  1734. +
  1735. + /* Most boards should use MLO_AN_INBAND, but existing boards don't have
  1736. + * a managed property. Default to MLO_AN_INBAND if nothing else is
  1737. + * specified. We need to be careful and not enable this if we have a
  1738. + * fixed link or if we are using MII or RGMII, since those
  1739. + * configurations modes don't use in-band autonegotiation.
  1740. + */
  1741. + fixed = of_get_child_by_name(mac_node, "fixed-link");
  1742. + if (!fixed && !of_property_read_bool(mac_node, "fixed-link") &&
  1743. + !of_property_read_bool(mac_node, "managed") &&
  1744. + mac_dev->phy_if != PHY_INTERFACE_MODE_MII &&
  1745. + !phy_interface_mode_is_rgmii(mac_dev->phy_if))
  1746. + mac_dev->phylink_config.ovr_an_inband = true;
  1747. + of_node_put(fixed);
  1748. +
  1749. err = memac_init(mac_dev->fman_mac);
  1750. if (err < 0)
  1751. - goto _return_fixed_link_free;
  1752. + goto _return_fm_mac_free;
  1753. dev_info(mac_dev->dev, "FMan MEMAC\n");
  1754. - goto _return;
  1755. + return 0;
  1756. -_return_phy_power_off:
  1757. - phy_power_off(memac->serdes);
  1758. -_return_phy_exit:
  1759. - phy_exit(memac->serdes);
  1760. -_return_fixed_link_free:
  1761. - kfree(fixed_link);
  1762. _return_fm_mac_free:
  1763. memac_free(mac_dev->fman_mac);
  1764. -_return:
  1765. return err;
  1766. }
  1767. --- a/drivers/net/ethernet/freescale/fman/fman_tgec.c
  1768. +++ b/drivers/net/ethernet/freescale/fman/fman_tgec.c
  1769. @@ -13,6 +13,7 @@
  1770. #include <linux/bitrev.h>
  1771. #include <linux/io.h>
  1772. #include <linux/crc32.h>
  1773. +#include <linux/netdevice.h>
  1774. /* Transmit Inter-Packet Gap Length Register (TX_IPG_LENGTH) */
  1775. #define TGEC_TX_IPG_LENGTH_MASK 0x000003ff
  1776. @@ -243,10 +244,6 @@ static int init(struct tgec_regs __iomem
  1777. static int check_init_parameters(struct fman_mac *tgec)
  1778. {
  1779. - if (tgec->max_speed < SPEED_10000) {
  1780. - pr_err("10G MAC driver only support 10G speed\n");
  1781. - return -EINVAL;
  1782. - }
  1783. if (!tgec->exception_cb) {
  1784. pr_err("uninitialized exception_cb\n");
  1785. return -EINVAL;
  1786. @@ -384,40 +381,13 @@ static void free_init_resources(struct f
  1787. tgec->unicast_addr_hash = NULL;
  1788. }
  1789. -static bool is_init_done(struct tgec_cfg *cfg)
  1790. -{
  1791. - /* Checks if tGEC driver parameters were initialized */
  1792. - if (!cfg)
  1793. - return true;
  1794. -
  1795. - return false;
  1796. -}
  1797. -
  1798. static int tgec_enable(struct fman_mac *tgec)
  1799. {
  1800. - struct tgec_regs __iomem *regs = tgec->regs;
  1801. - u32 tmp;
  1802. -
  1803. - if (!is_init_done(tgec->cfg))
  1804. - return -EINVAL;
  1805. -
  1806. - tmp = ioread32be(&regs->command_config);
  1807. - tmp |= CMD_CFG_RX_EN | CMD_CFG_TX_EN;
  1808. - iowrite32be(tmp, &regs->command_config);
  1809. -
  1810. return 0;
  1811. }
  1812. static void tgec_disable(struct fman_mac *tgec)
  1813. {
  1814. - struct tgec_regs __iomem *regs = tgec->regs;
  1815. - u32 tmp;
  1816. -
  1817. - WARN_ON_ONCE(!is_init_done(tgec->cfg));
  1818. -
  1819. - tmp = ioread32be(&regs->command_config);
  1820. - tmp &= ~(CMD_CFG_RX_EN | CMD_CFG_TX_EN);
  1821. - iowrite32be(tmp, &regs->command_config);
  1822. }
  1823. static int tgec_set_promiscuous(struct fman_mac *tgec, bool new_val)
  1824. @@ -425,9 +395,6 @@ static int tgec_set_promiscuous(struct f
  1825. struct tgec_regs __iomem *regs = tgec->regs;
  1826. u32 tmp;
  1827. - if (!is_init_done(tgec->cfg))
  1828. - return -EINVAL;
  1829. -
  1830. tmp = ioread32be(&regs->command_config);
  1831. if (new_val)
  1832. tmp |= CMD_CFG_PROMIS_EN;
  1833. @@ -444,9 +411,6 @@ static int tgec_set_tx_pause_frames(stru
  1834. {
  1835. struct tgec_regs __iomem *regs = tgec->regs;
  1836. - if (!is_init_done(tgec->cfg))
  1837. - return -EINVAL;
  1838. -
  1839. iowrite32be((u32)pause_time, &regs->pause_quant);
  1840. return 0;
  1841. @@ -457,9 +421,6 @@ static int tgec_accept_rx_pause_frames(s
  1842. struct tgec_regs __iomem *regs = tgec->regs;
  1843. u32 tmp;
  1844. - if (!is_init_done(tgec->cfg))
  1845. - return -EINVAL;
  1846. -
  1847. tmp = ioread32be(&regs->command_config);
  1848. if (!en)
  1849. tmp |= CMD_CFG_PAUSE_IGNORE;
  1850. @@ -470,12 +431,53 @@ static int tgec_accept_rx_pause_frames(s
  1851. return 0;
  1852. }
  1853. +static void tgec_mac_config(struct phylink_config *config, unsigned int mode,
  1854. + const struct phylink_link_state *state)
  1855. +{
  1856. +}
  1857. +
  1858. +static void tgec_link_up(struct phylink_config *config, struct phy_device *phy,
  1859. + unsigned int mode, phy_interface_t interface,
  1860. + int speed, int duplex, bool tx_pause, bool rx_pause)
  1861. +{
  1862. + struct mac_device *mac_dev = fman_config_to_mac(config);
  1863. + struct fman_mac *tgec = mac_dev->fman_mac;
  1864. + struct tgec_regs __iomem *regs = tgec->regs;
  1865. + u16 pause_time = tx_pause ? FSL_FM_PAUSE_TIME_ENABLE :
  1866. + FSL_FM_PAUSE_TIME_DISABLE;
  1867. + u32 tmp;
  1868. +
  1869. + tgec_set_tx_pause_frames(tgec, 0, pause_time, 0);
  1870. + tgec_accept_rx_pause_frames(tgec, rx_pause);
  1871. + mac_dev->update_speed(mac_dev, speed);
  1872. +
  1873. + tmp = ioread32be(&regs->command_config);
  1874. + tmp |= CMD_CFG_RX_EN | CMD_CFG_TX_EN;
  1875. + iowrite32be(tmp, &regs->command_config);
  1876. +}
  1877. +
  1878. +static void tgec_link_down(struct phylink_config *config, unsigned int mode,
  1879. + phy_interface_t interface)
  1880. +{
  1881. + struct fman_mac *tgec = fman_config_to_mac(config)->fman_mac;
  1882. + struct tgec_regs __iomem *regs = tgec->regs;
  1883. + u32 tmp;
  1884. +
  1885. + tmp = ioread32be(&regs->command_config);
  1886. + tmp &= ~(CMD_CFG_RX_EN | CMD_CFG_TX_EN);
  1887. + iowrite32be(tmp, &regs->command_config);
  1888. +}
  1889. +
  1890. +static const struct phylink_mac_ops tgec_mac_ops = {
  1891. + .validate = phylink_generic_validate,
  1892. + .mac_config = tgec_mac_config,
  1893. + .mac_link_up = tgec_link_up,
  1894. + .mac_link_down = tgec_link_down,
  1895. +};
  1896. +
  1897. static int tgec_modify_mac_address(struct fman_mac *tgec,
  1898. const enet_addr_t *p_enet_addr)
  1899. {
  1900. - if (!is_init_done(tgec->cfg))
  1901. - return -EINVAL;
  1902. -
  1903. tgec->addr = ENET_ADDR_TO_UINT64(*p_enet_addr);
  1904. set_mac_address(tgec->regs, (const u8 *)(*p_enet_addr));
  1905. @@ -490,9 +492,6 @@ static int tgec_add_hash_mac_address(str
  1906. u32 crc = 0xFFFFFFFF, hash;
  1907. u64 addr;
  1908. - if (!is_init_done(tgec->cfg))
  1909. - return -EINVAL;
  1910. -
  1911. addr = ENET_ADDR_TO_UINT64(*eth_addr);
  1912. if (!(addr & GROUP_ADDRESS)) {
  1913. @@ -525,9 +524,6 @@ static int tgec_set_allmulti(struct fman
  1914. u32 entry;
  1915. struct tgec_regs __iomem *regs = tgec->regs;
  1916. - if (!is_init_done(tgec->cfg))
  1917. - return -EINVAL;
  1918. -
  1919. if (enable) {
  1920. for (entry = 0; entry < TGEC_HASH_TABLE_SIZE; entry++)
  1921. iowrite32be(entry | TGEC_HASH_MCAST_EN,
  1922. @@ -548,9 +544,6 @@ static int tgec_set_tstamp(struct fman_m
  1923. struct tgec_regs __iomem *regs = tgec->regs;
  1924. u32 tmp;
  1925. - if (!is_init_done(tgec->cfg))
  1926. - return -EINVAL;
  1927. -
  1928. tmp = ioread32be(&regs->command_config);
  1929. if (enable)
  1930. @@ -572,9 +565,6 @@ static int tgec_del_hash_mac_address(str
  1931. u32 crc = 0xFFFFFFFF, hash;
  1932. u64 addr;
  1933. - if (!is_init_done(tgec->cfg))
  1934. - return -EINVAL;
  1935. -
  1936. addr = ((*(u64 *)eth_addr) >> 16);
  1937. /* CRC calculation */
  1938. @@ -601,22 +591,12 @@ static int tgec_del_hash_mac_address(str
  1939. return 0;
  1940. }
  1941. -static void tgec_adjust_link(struct mac_device *mac_dev)
  1942. -{
  1943. - struct phy_device *phy_dev = mac_dev->phy_dev;
  1944. -
  1945. - mac_dev->update_speed(mac_dev, phy_dev->speed);
  1946. -}
  1947. -
  1948. static int tgec_set_exception(struct fman_mac *tgec,
  1949. enum fman_mac_exceptions exception, bool enable)
  1950. {
  1951. struct tgec_regs __iomem *regs = tgec->regs;
  1952. u32 bit_mask = 0;
  1953. - if (!is_init_done(tgec->cfg))
  1954. - return -EINVAL;
  1955. -
  1956. bit_mask = get_exception_flag(exception);
  1957. if (bit_mask) {
  1958. if (enable)
  1959. @@ -641,9 +621,6 @@ static int tgec_init(struct fman_mac *tg
  1960. enet_addr_t eth_addr;
  1961. int err;
  1962. - if (is_init_done(tgec->cfg))
  1963. - return -EINVAL;
  1964. -
  1965. if (DEFAULT_RESET_ON_INIT &&
  1966. (fman_reset_mac(tgec->fm, tgec->mac_id) != 0)) {
  1967. pr_err("Can't reset MAC!\n");
  1968. @@ -753,7 +730,6 @@ static struct fman_mac *tgec_config(stru
  1969. tgec->regs = mac_dev->vaddr;
  1970. tgec->addr = ENET_ADDR_TO_UINT64(mac_dev->addr);
  1971. - tgec->max_speed = params->max_speed;
  1972. tgec->mac_id = params->mac_id;
  1973. tgec->exceptions = (TGEC_IMASK_MDIO_SCAN_EVENT |
  1974. TGEC_IMASK_REM_FAULT |
  1975. @@ -788,17 +764,15 @@ int tgec_initialization(struct mac_devic
  1976. int err;
  1977. struct fman_mac *tgec;
  1978. + mac_dev->phylink_ops = &tgec_mac_ops;
  1979. mac_dev->set_promisc = tgec_set_promiscuous;
  1980. mac_dev->change_addr = tgec_modify_mac_address;
  1981. mac_dev->add_hash_mac_addr = tgec_add_hash_mac_address;
  1982. mac_dev->remove_hash_mac_addr = tgec_del_hash_mac_address;
  1983. - mac_dev->set_tx_pause = tgec_set_tx_pause_frames;
  1984. - mac_dev->set_rx_pause = tgec_accept_rx_pause_frames;
  1985. mac_dev->set_exception = tgec_set_exception;
  1986. mac_dev->set_allmulti = tgec_set_allmulti;
  1987. mac_dev->set_tstamp = tgec_set_tstamp;
  1988. mac_dev->set_multi = fman_set_multi;
  1989. - mac_dev->adjust_link = tgec_adjust_link;
  1990. mac_dev->enable = tgec_enable;
  1991. mac_dev->disable = tgec_disable;
  1992. @@ -808,6 +782,19 @@ int tgec_initialization(struct mac_devic
  1993. goto _return;
  1994. }
  1995. + /* The internal connection to the serdes is XGMII, but this isn't
  1996. + * really correct for the phy mode (which is the external connection).
  1997. + * However, this is how all older device trees say that they want
  1998. + * XAUI, so just convert it for them.
  1999. + */
  2000. + if (mac_dev->phy_if == PHY_INTERFACE_MODE_XGMII)
  2001. + mac_dev->phy_if = PHY_INTERFACE_MODE_XAUI;
  2002. +
  2003. + __set_bit(PHY_INTERFACE_MODE_XAUI,
  2004. + mac_dev->phylink_config.supported_interfaces);
  2005. + mac_dev->phylink_config.mac_capabilities =
  2006. + MAC_SYM_PAUSE | MAC_ASYM_PAUSE | MAC_10000FD;
  2007. +
  2008. tgec = mac_dev->fman_mac;
  2009. tgec->cfg->max_frame_length = fman_get_max_frm();
  2010. err = tgec_init(tgec);
  2011. --- a/drivers/net/ethernet/freescale/fman/mac.c
  2012. +++ b/drivers/net/ethernet/freescale/fman/mac.c
  2013. @@ -15,6 +15,7 @@
  2014. #include <linux/phy.h>
  2015. #include <linux/netdevice.h>
  2016. #include <linux/phy_fixed.h>
  2017. +#include <linux/phylink.h>
  2018. #include <linux/etherdevice.h>
  2019. #include <linux/libfdt_env.h>
  2020. @@ -93,130 +94,8 @@ int fman_set_multi(struct net_device *ne
  2021. return 0;
  2022. }
  2023. -/**
  2024. - * fman_set_mac_active_pause
  2025. - * @mac_dev: A pointer to the MAC device
  2026. - * @rx: Pause frame setting for RX
  2027. - * @tx: Pause frame setting for TX
  2028. - *
  2029. - * Set the MAC RX/TX PAUSE frames settings
  2030. - *
  2031. - * Avoid redundant calls to FMD, if the MAC driver already contains the desired
  2032. - * active PAUSE settings. Otherwise, the new active settings should be reflected
  2033. - * in FMan.
  2034. - *
  2035. - * Return: 0 on success; Error code otherwise.
  2036. - */
  2037. -int fman_set_mac_active_pause(struct mac_device *mac_dev, bool rx, bool tx)
  2038. -{
  2039. - struct fman_mac *fman_mac = mac_dev->fman_mac;
  2040. - int err = 0;
  2041. -
  2042. - if (rx != mac_dev->rx_pause_active) {
  2043. - err = mac_dev->set_rx_pause(fman_mac, rx);
  2044. - if (likely(err == 0))
  2045. - mac_dev->rx_pause_active = rx;
  2046. - }
  2047. -
  2048. - if (tx != mac_dev->tx_pause_active) {
  2049. - u16 pause_time = (tx ? FSL_FM_PAUSE_TIME_ENABLE :
  2050. - FSL_FM_PAUSE_TIME_DISABLE);
  2051. -
  2052. - err = mac_dev->set_tx_pause(fman_mac, 0, pause_time, 0);
  2053. -
  2054. - if (likely(err == 0))
  2055. - mac_dev->tx_pause_active = tx;
  2056. - }
  2057. -
  2058. - return err;
  2059. -}
  2060. -EXPORT_SYMBOL(fman_set_mac_active_pause);
  2061. -
  2062. -/**
  2063. - * fman_get_pause_cfg
  2064. - * @mac_dev: A pointer to the MAC device
  2065. - * @rx_pause: Return value for RX setting
  2066. - * @tx_pause: Return value for TX setting
  2067. - *
  2068. - * Determine the MAC RX/TX PAUSE frames settings based on PHY
  2069. - * autonegotiation or values set by eththool.
  2070. - *
  2071. - * Return: Pointer to FMan device.
  2072. - */
  2073. -void fman_get_pause_cfg(struct mac_device *mac_dev, bool *rx_pause,
  2074. - bool *tx_pause)
  2075. -{
  2076. - struct phy_device *phy_dev = mac_dev->phy_dev;
  2077. - u16 lcl_adv, rmt_adv;
  2078. - u8 flowctrl;
  2079. -
  2080. - *rx_pause = *tx_pause = false;
  2081. -
  2082. - if (!phy_dev->duplex)
  2083. - return;
  2084. -
  2085. - /* If PAUSE autonegotiation is disabled, the TX/RX PAUSE settings
  2086. - * are those set by ethtool.
  2087. - */
  2088. - if (!mac_dev->autoneg_pause) {
  2089. - *rx_pause = mac_dev->rx_pause_req;
  2090. - *tx_pause = mac_dev->tx_pause_req;
  2091. - return;
  2092. - }
  2093. -
  2094. - /* Else if PAUSE autonegotiation is enabled, the TX/RX PAUSE
  2095. - * settings depend on the result of the link negotiation.
  2096. - */
  2097. -
  2098. - /* get local capabilities */
  2099. - lcl_adv = linkmode_adv_to_lcl_adv_t(phy_dev->advertising);
  2100. -
  2101. - /* get link partner capabilities */
  2102. - rmt_adv = 0;
  2103. - if (phy_dev->pause)
  2104. - rmt_adv |= LPA_PAUSE_CAP;
  2105. - if (phy_dev->asym_pause)
  2106. - rmt_adv |= LPA_PAUSE_ASYM;
  2107. -
  2108. - /* Calculate TX/RX settings based on local and peer advertised
  2109. - * symmetric/asymmetric PAUSE capabilities.
  2110. - */
  2111. - flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
  2112. - if (flowctrl & FLOW_CTRL_RX)
  2113. - *rx_pause = true;
  2114. - if (flowctrl & FLOW_CTRL_TX)
  2115. - *tx_pause = true;
  2116. -}
  2117. -EXPORT_SYMBOL(fman_get_pause_cfg);
  2118. -
  2119. -#define DTSEC_SUPPORTED \
  2120. - (SUPPORTED_10baseT_Half \
  2121. - | SUPPORTED_10baseT_Full \
  2122. - | SUPPORTED_100baseT_Half \
  2123. - | SUPPORTED_100baseT_Full \
  2124. - | SUPPORTED_Autoneg \
  2125. - | SUPPORTED_Pause \
  2126. - | SUPPORTED_Asym_Pause \
  2127. - | SUPPORTED_FIBRE \
  2128. - | SUPPORTED_MII)
  2129. -
  2130. static DEFINE_MUTEX(eth_lock);
  2131. -static const u16 phy2speed[] = {
  2132. - [PHY_INTERFACE_MODE_MII] = SPEED_100,
  2133. - [PHY_INTERFACE_MODE_GMII] = SPEED_1000,
  2134. - [PHY_INTERFACE_MODE_SGMII] = SPEED_1000,
  2135. - [PHY_INTERFACE_MODE_TBI] = SPEED_1000,
  2136. - [PHY_INTERFACE_MODE_RMII] = SPEED_100,
  2137. - [PHY_INTERFACE_MODE_RGMII] = SPEED_1000,
  2138. - [PHY_INTERFACE_MODE_RGMII_ID] = SPEED_1000,
  2139. - [PHY_INTERFACE_MODE_RGMII_RXID] = SPEED_1000,
  2140. - [PHY_INTERFACE_MODE_RGMII_TXID] = SPEED_1000,
  2141. - [PHY_INTERFACE_MODE_RTBI] = SPEED_1000,
  2142. - [PHY_INTERFACE_MODE_QSGMII] = SPEED_1000,
  2143. - [PHY_INTERFACE_MODE_XGMII] = SPEED_10000
  2144. -};
  2145. -
  2146. static struct platform_device *dpaa_eth_add_device(int fman_id,
  2147. struct mac_device *mac_dev)
  2148. {
  2149. @@ -263,8 +142,8 @@ no_mem:
  2150. }
  2151. static const struct of_device_id mac_match[] = {
  2152. - { .compatible = "fsl,fman-dtsec", .data = dtsec_initialization },
  2153. - { .compatible = "fsl,fman-xgec", .data = tgec_initialization },
  2154. + { .compatible = "fsl,fman-dtsec", .data = dtsec_initialization },
  2155. + { .compatible = "fsl,fman-xgec", .data = tgec_initialization },
  2156. { .compatible = "fsl,fman-memac", .data = memac_initialization },
  2157. {}
  2158. };
  2159. @@ -295,6 +174,7 @@ static int mac_probe(struct platform_dev
  2160. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  2161. if (!priv)
  2162. return -ENOMEM;
  2163. + platform_set_drvdata(_of_dev, mac_dev);
  2164. /* Save private information */
  2165. mac_dev->priv = priv;
  2166. @@ -424,57 +304,21 @@ static int mac_probe(struct platform_dev
  2167. }
  2168. mac_dev->phy_if = phy_if;
  2169. - priv->speed = phy2speed[mac_dev->phy_if];
  2170. - params.max_speed = priv->speed;
  2171. - mac_dev->if_support = DTSEC_SUPPORTED;
  2172. - /* We don't support half-duplex in SGMII mode */
  2173. - if (mac_dev->phy_if == PHY_INTERFACE_MODE_SGMII)
  2174. - mac_dev->if_support &= ~(SUPPORTED_10baseT_Half |
  2175. - SUPPORTED_100baseT_Half);
  2176. -
  2177. - /* Gigabit support (no half-duplex) */
  2178. - if (params.max_speed == 1000)
  2179. - mac_dev->if_support |= SUPPORTED_1000baseT_Full;
  2180. -
  2181. - /* The 10G interface only supports one mode */
  2182. - if (mac_dev->phy_if == PHY_INTERFACE_MODE_XGMII)
  2183. - mac_dev->if_support = SUPPORTED_10000baseT_Full;
  2184. -
  2185. - /* Get the rest of the PHY information */
  2186. - mac_dev->phy_node = of_parse_phandle(mac_node, "phy-handle", 0);
  2187. -
  2188. - params.basex_if = false;
  2189. params.mac_id = priv->cell_index;
  2190. params.fm = (void *)priv->fman;
  2191. params.exception_cb = mac_exception;
  2192. params.event_cb = mac_exception;
  2193. err = init(mac_dev, mac_node, &params);
  2194. - if (err < 0) {
  2195. - dev_err(dev, "mac_dev->init() = %d\n", err);
  2196. - of_node_put(mac_dev->phy_node);
  2197. - return err;
  2198. - }
  2199. -
  2200. - /* pause frame autonegotiation enabled */
  2201. - mac_dev->autoneg_pause = true;
  2202. -
  2203. - /* By intializing the values to false, force FMD to enable PAUSE frames
  2204. - * on RX and TX
  2205. - */
  2206. - mac_dev->rx_pause_req = true;
  2207. - mac_dev->tx_pause_req = true;
  2208. - mac_dev->rx_pause_active = false;
  2209. - mac_dev->tx_pause_active = false;
  2210. - err = fman_set_mac_active_pause(mac_dev, true, true);
  2211. if (err < 0)
  2212. - dev_err(dev, "fman_set_mac_active_pause() = %d\n", err);
  2213. + return err;
  2214. if (!is_zero_ether_addr(mac_dev->addr))
  2215. dev_info(dev, "FMan MAC address: %pM\n", mac_dev->addr);
  2216. priv->eth_dev = dpaa_eth_add_device(fman_id, mac_dev);
  2217. if (IS_ERR(priv->eth_dev)) {
  2218. + err = PTR_ERR(priv->eth_dev);
  2219. dev_err(dev, "failed to add Ethernet platform device for MAC %d\n",
  2220. priv->cell_index);
  2221. priv->eth_dev = NULL;
  2222. --- a/drivers/net/ethernet/freescale/fman/mac.h
  2223. +++ b/drivers/net/ethernet/freescale/fman/mac.h
  2224. @@ -9,6 +9,7 @@
  2225. #include <linux/device.h>
  2226. #include <linux/if_ether.h>
  2227. #include <linux/phy.h>
  2228. +#include <linux/phylink.h>
  2229. #include <linux/list.h>
  2230. #include "fman_port.h"
  2231. @@ -24,32 +25,22 @@ struct mac_device {
  2232. struct resource *res;
  2233. u8 addr[ETH_ALEN];
  2234. struct fman_port *port[2];
  2235. - u32 if_support;
  2236. - struct phy_device *phy_dev;
  2237. + struct phylink *phylink;
  2238. + struct phylink_config phylink_config;
  2239. phy_interface_t phy_if;
  2240. - struct device_node *phy_node;
  2241. - struct net_device *net_dev;
  2242. - bool autoneg_pause;
  2243. - bool rx_pause_req;
  2244. - bool tx_pause_req;
  2245. - bool rx_pause_active;
  2246. - bool tx_pause_active;
  2247. bool promisc;
  2248. bool allmulti;
  2249. + const struct phylink_mac_ops *phylink_ops;
  2250. int (*enable)(struct fman_mac *mac_dev);
  2251. void (*disable)(struct fman_mac *mac_dev);
  2252. - void (*adjust_link)(struct mac_device *mac_dev);
  2253. int (*set_promisc)(struct fman_mac *mac_dev, bool enable);
  2254. int (*change_addr)(struct fman_mac *mac_dev, const enet_addr_t *enet_addr);
  2255. int (*set_allmulti)(struct fman_mac *mac_dev, bool enable);
  2256. int (*set_tstamp)(struct fman_mac *mac_dev, bool enable);
  2257. int (*set_multi)(struct net_device *net_dev,
  2258. struct mac_device *mac_dev);
  2259. - int (*set_rx_pause)(struct fman_mac *mac_dev, bool en);
  2260. - int (*set_tx_pause)(struct fman_mac *mac_dev, u8 priority,
  2261. - u16 pause_time, u16 thresh_time);
  2262. int (*set_exception)(struct fman_mac *mac_dev,
  2263. enum fman_mac_exceptions exception, bool enable);
  2264. int (*add_hash_mac_addr)(struct fman_mac *mac_dev,
  2265. @@ -63,6 +54,12 @@ struct mac_device {
  2266. struct mac_priv_s *priv;
  2267. };
  2268. +static inline struct mac_device
  2269. +*fman_config_to_mac(struct phylink_config *config)
  2270. +{
  2271. + return container_of(config, struct mac_device, phylink_config);
  2272. +}
  2273. +
  2274. struct dpaa_eth_data {
  2275. struct mac_device *mac_dev;
  2276. int mac_hw_id;