082-ipq8064-dtsi-tweaks.patch 5.9 KB

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  1. --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
  2. +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
  3. @@ -352,6 +352,7 @@
  4. gpio-ranges = <&qcom_pinmux 0 0 69>;
  5. #gpio-cells = <2>;
  6. interrupt-controller;
  7. + #address-cells = <0>;
  8. #interrupt-cells = <2>;
  9. interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
  10. @@ -379,6 +380,7 @@
  11. function = "pcie3_rst";
  12. drive-strength = <12>;
  13. bias-disable;
  14. + output-low;
  15. };
  16. };
  17. @@ -411,12 +413,9 @@
  18. };
  19. nand_pins: nand_pins {
  20. - mux {
  21. + disable {
  22. pins = "gpio34", "gpio35", "gpio36",
  23. - "gpio37", "gpio38", "gpio39",
  24. - "gpio40", "gpio41", "gpio42",
  25. - "gpio43", "gpio44", "gpio45",
  26. - "gpio46", "gpio47";
  27. + "gpio37", "gpio38";
  28. function = "nand";
  29. drive-strength = <10>;
  30. bias-disable;
  31. @@ -424,6 +423,8 @@
  32. pullups {
  33. pins = "gpio39";
  34. + function = "nand";
  35. + drive-strength = <10>;
  36. bias-pull-up;
  37. };
  38. @@ -431,6 +432,8 @@
  39. pins = "gpio40", "gpio41", "gpio42",
  40. "gpio43", "gpio44", "gpio45",
  41. "gpio46", "gpio47";
  42. + function = "nand";
  43. + drive-strength = <10>;
  44. bias-bus-hold;
  45. };
  46. };
  47. @@ -439,6 +442,7 @@
  48. intc: interrupt-controller@2000000 {
  49. compatible = "qcom,msm-qgic2";
  50. interrupt-controller;
  51. + #address-cells = <0>;
  52. #interrupt-cells = <3>;
  53. reg = <0x02000000 0x1000>,
  54. <0x02002000 0x1000>;
  55. @@ -468,11 +472,13 @@
  56. acc0: clock-controller@2088000 {
  57. compatible = "qcom,kpss-acc-v1";
  58. reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
  59. + clock-output-names = "acpu0_aux";
  60. };
  61. acc1: clock-controller@2098000 {
  62. compatible = "qcom,kpss-acc-v1";
  63. reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
  64. + clock-output-names = "acpu1_aux";
  65. };
  66. adm_dma: dma-controller@18300000 {
  67. @@ -496,13 +502,13 @@
  68. };
  69. saw0: regulator@2089000 {
  70. - compatible = "qcom,saw2";
  71. + compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
  72. reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
  73. regulator;
  74. };
  75. saw1: regulator@2099000 {
  76. - compatible = "qcom,saw2";
  77. + compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
  78. reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
  79. regulator;
  80. };
  81. @@ -533,7 +533,7 @@
  82. status = "disabled";
  83. };
  84. - i2c@124a0000 {
  85. + gsbi2_i2c: i2c@124a0000 {
  86. compatible = "qcom,i2c-qup-v1.1.1";
  87. reg = <0x124a0000 0x1000>;
  88. interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
  89. @@ -676,9 +682,6 @@
  90. compatible = "qcom,ipq806x-nand";
  91. reg = <0x1ac00000 0x800>;
  92. - pinctrl-0 = <&nand_pins>;
  93. - pinctrl-names = "default";
  94. -
  95. clocks = <&gcc EBI2_CLK>,
  96. <&gcc EBI2_AON_CLK>;
  97. clock-names = "core", "aon";
  98. @@ -733,10 +736,13 @@
  99. tsens_calib_backup: calib_backup@410 {
  100. reg = <0x410 0xb>;
  101. };
  102. + speedbin_efuse: speedbin@0c0 {
  103. + reg = <0x0c0 0x4>;
  104. + };
  105. };
  106. gcc: clock-controller@900000 {
  107. - compatible = "qcom,gcc-ipq8064";
  108. + compatible = "qcom,gcc-ipq8064", "syscon";
  109. reg = <0x00900000 0x4000>;
  110. #clock-cells = <1>;
  111. #reset-cells = <1>;
  112. @@ -768,10 +774,45 @@
  113. clocks = <&gcc RPM_MSG_RAM_H_CLK>;
  114. clock-names = "ram";
  115. + #address-cells = <1>;
  116. + #size-cells = <0>;
  117. +
  118. rpmcc: clock-controller {
  119. compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
  120. #clock-cells = <1>;
  121. };
  122. +
  123. + regulators {
  124. + compatible = "qcom,rpm-smb208-regulators";
  125. +
  126. + smb208_s1a: s1a {
  127. + regulator-min-microvolt = <1050000>;
  128. + regulator-max-microvolt = <1150000>;
  129. +
  130. + qcom,switch-mode-frequency = <1200000>;
  131. + };
  132. +
  133. + smb208_s1b: s1b {
  134. + regulator-min-microvolt = <1050000>;
  135. + regulator-max-microvolt = <1150000>;
  136. +
  137. + qcom,switch-mode-frequency = <1200000>;
  138. + };
  139. +
  140. + smb208_s2a: s2a {
  141. + regulator-min-microvolt = < 800000>;
  142. + regulator-max-microvolt = <1250000>;
  143. +
  144. + qcom,switch-mode-frequency = <1200000>;
  145. + };
  146. +
  147. + smb208_s2b: s2b {
  148. + regulator-min-microvolt = < 800000>;
  149. + regulator-max-microvolt = <1250000>;
  150. +
  151. + qcom,switch-mode-frequency = <1200000>;
  152. + };
  153. + };
  154. };
  155. tcsr: syscon@1a400000 {
  156. @@ -965,7 +1006,7 @@
  157. gmac0: ethernet@37000000 {
  158. device_type = "network";
  159. - compatible = "qcom,ipq806x-gmac";
  160. + compatible = "qcom,ipq806x-gmac", "snps,dwmac";
  161. reg = <0x37000000 0x200000>;
  162. interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
  163. interrupt-names = "macirq";
  164. @@ -989,7 +1030,7 @@
  165. gmac1: ethernet@37200000 {
  166. device_type = "network";
  167. - compatible = "qcom,ipq806x-gmac";
  168. + compatible = "qcom,ipq806x-gmac", "snps,dwmac";
  169. reg = <0x37200000 0x200000>;
  170. interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
  171. interrupt-names = "macirq";
  172. @@ -1013,7 +1054,7 @@
  173. gmac2: ethernet@37400000 {
  174. device_type = "network";
  175. - compatible = "qcom,ipq806x-gmac";
  176. + compatible = "qcom,ipq806x-gmac", "snps,dwmac";
  177. reg = <0x37400000 0x200000>;
  178. interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
  179. interrupt-names = "macirq";
  180. @@ -1037,7 +1078,7 @@
  181. gmac3: ethernet@37600000 {
  182. device_type = "network";
  183. - compatible = "qcom,ipq806x-gmac";
  184. + compatible = "qcom,ipq806x-gmac", "snps,dwmac";
  185. reg = <0x37600000 0x200000>;
  186. interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
  187. interrupt-names = "macirq";
  188. @@ -1050,8 +1050,6 @@
  189. clocks = <&gcc USB30_0_UTMI_CLK>;
  190. clock-names = "ref";
  191. #phy-cells = <0>;
  192. -
  193. - status = "disabled";
  194. };
  195. ss_phy_0: usb3phy@100f8830 {
  196. @@ -1055,8 +1055,6 @@
  197. clocks = <&gcc USB30_0_MASTER_CLK>;
  198. clock-names = "ref";
  199. #phy-cells = <0>;
  200. -
  201. - status = "disabled";
  202. };
  203. usb3_0: usb3@100f8800 {
  204. @@ -1176,7 +1217,7 @@
  205. };
  206. amba: amba {
  207. - compatible = "simple-bus";
  208. + compatible = "arm,amba-bus";
  209. #address-cells = <1>;
  210. #size-cells = <1>;
  211. ranges;
  212. @@ -1195,7 +1236,6 @@
  213. non-removable;
  214. cap-sd-highspeed;
  215. cap-mmc-highspeed;
  216. - mmc-ddr-1_8v;
  217. vmmc-supply = <&vsdcc_fixed>;
  218. dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
  219. dma-names = "tx", "rx";