qcom-ipq4018-ex61x0v2.dtsi 6.3 KB

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  1. /* Copyright (c) 2015, The Linux Foundation. All rights reserved.
  2. * Copyright (c) 2018, David Bauer <[email protected]>
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. *
  16. */
  17. #include "qcom-ipq4019.dtsi"
  18. #include <dt-bindings/gpio/gpio.h>
  19. #include <dt-bindings/input/input.h>
  20. #include <dt-bindings/soc/qcom,tcsr.h>
  21. / {
  22. model = "Netgear EX61X0v2";
  23. compatible = "netgear,ex61x0v2";
  24. soc {
  25. rng@22000 {
  26. status = "okay";
  27. };
  28. mdio@90000 {
  29. status = "okay";
  30. };
  31. ess-psgmii@98000 {
  32. status = "okay";
  33. };
  34. tcsr@1949000 {
  35. compatible = "qcom,tcsr";
  36. reg = <0x1949000 0x100>;
  37. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  38. };
  39. ess_tcsr@1953000 {
  40. compatible = "qcom,tcsr";
  41. reg = <0x1953000 0x1000>;
  42. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  43. };
  44. tcsr@1957000 {
  45. compatible = "qcom,tcsr";
  46. reg = <0x1957000 0x100>;
  47. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  48. };
  49. crypto@8e3a000 {
  50. status = "okay";
  51. };
  52. watchdog@b017000 {
  53. status = "okay";
  54. };
  55. ess-switch@c000000 {
  56. status = "okay";
  57. };
  58. edma@c080000 {
  59. status = "okay";
  60. qcom,num_gmac = <1>;
  61. };
  62. };
  63. aliases {
  64. led-boot = &power_amber;
  65. led-failsafe = &power_amber;
  66. led-running = &power_green;
  67. led-upgrade = &power_amber;
  68. label-mac-device = &gmac0;
  69. };
  70. keys {
  71. compatible = "gpio-keys";
  72. wps {
  73. label = "wps";
  74. gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
  75. linux,code = <KEY_WPS_BUTTON>;
  76. };
  77. reset {
  78. label = "reset";
  79. gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
  80. linux,code = <KEY_RESTART>;
  81. };
  82. };
  83. led_spi {
  84. compatible = "spi-gpio";
  85. #address-cells = <1>;
  86. #size-cells = <0>;
  87. sck-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
  88. mosi-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
  89. num-chipselects = <0>;
  90. led_gpio: led_gpio@0 {
  91. compatible = "fairchild,74hc595";
  92. reg = <0>;
  93. gpio-controller;
  94. #gpio-cells = <2>;
  95. registers-number = <1>;
  96. spi-max-frequency = <1000000>;
  97. };
  98. };
  99. leds {
  100. compatible = "gpio-leds";
  101. power_amber: power_amber {
  102. label = "amber:power";
  103. gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;
  104. };
  105. power_green: power_green {
  106. label = "green:power";
  107. gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
  108. };
  109. right {
  110. label = "blue:right";
  111. gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
  112. };
  113. left {
  114. label = "blue:left";
  115. gpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;
  116. };
  117. client_green {
  118. label = "green:client";
  119. gpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;
  120. };
  121. client_red {
  122. label = "red:client";
  123. gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
  124. };
  125. router_green {
  126. label = "green:router";
  127. gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
  128. };
  129. router_red {
  130. label = "red:router";
  131. gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
  132. };
  133. wps {
  134. label = "green:wps";
  135. gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
  136. };
  137. };
  138. };
  139. &tlmm {
  140. serial_pins: serial_pinmux {
  141. mux {
  142. pins = "gpio60", "gpio61";
  143. function = "blsp_uart0";
  144. bias-disable;
  145. };
  146. };
  147. spi_0_pins: spi_0_pinmux {
  148. pin {
  149. function = "blsp_spi0";
  150. pins = "gpio55", "gpio56", "gpio57";
  151. drive-strength = <12>;
  152. bias-disable;
  153. };
  154. pin_cs {
  155. function = "gpio";
  156. pins = "gpio54";
  157. drive-strength = <2>;
  158. bias-disable;
  159. output-high;
  160. };
  161. };
  162. };
  163. &blsp1_spi1 {
  164. pinctrl-0 = <&spi_0_pins>;
  165. pinctrl-names = "default";
  166. status = "okay";
  167. cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
  168. mx25l12805d@0 {
  169. compatible = "jedec,spi-nor";
  170. reg = <0>;
  171. spi-max-frequency = <45000000>;
  172. partitions {
  173. compatible = "fixed-partitions";
  174. #address-cells = <1>;
  175. #size-cells = <1>;
  176. partition0@0 {
  177. label = "SBL1";
  178. reg = <0x00000000 0x00040000>;
  179. read-only;
  180. };
  181. partition1@40000 {
  182. label = "MIBIB";
  183. reg = <0x00040000 0x00020000>;
  184. read-only;
  185. };
  186. partition2@60000 {
  187. label = "QSEE";
  188. reg = <0x00060000 0x00060000>;
  189. read-only;
  190. };
  191. partition3@c0000 {
  192. label = "CDT";
  193. reg = <0x000c0000 0x00010000>;
  194. read-only;
  195. };
  196. partition4@d0000 {
  197. label = "DDRPARAMS";
  198. reg = <0x000d0000 0x00010000>;
  199. read-only;
  200. };
  201. partition5@E0000 {
  202. label = "APPSBLENV";
  203. reg = <0x000e0000 0x00010000>;
  204. read-only;
  205. };
  206. partition6@F0000 {
  207. label = "APPSBL";
  208. reg = <0x000f0000 0x00080000>;
  209. read-only;
  210. };
  211. partition7@170000 {
  212. label = "ART";
  213. reg = <0x00170000 0x00010000>;
  214. compatible = "nvmem-cells";
  215. read-only;
  216. #address-cells = <1>;
  217. #size-cells = <1>;
  218. precal_art_1000: precal@1000 {
  219. reg = <0x1000 0x2f20>;
  220. };
  221. precal_art_5000: precal@5000 {
  222. reg = <0x5000 0x2f20>;
  223. };
  224. };
  225. partition8@180000 {
  226. label = "config";
  227. reg = <0x00180000 0x00010000>;
  228. read-only;
  229. };
  230. partition9@190000 {
  231. label = "pot";
  232. reg = <0x00190000 0x00010000>;
  233. read-only;
  234. };
  235. partition10@1a0000 {
  236. compatible = "nvmem-cells";
  237. label = "dnidata";
  238. reg = <0x001a0000 0x00010000>;
  239. read-only;
  240. #address-cells = <1>;
  241. #size-cells = <1>;
  242. macaddr_dnidata_0: macaddr@0 {
  243. reg = <0x0 0x6>;
  244. };
  245. macaddr_dnidata_c: macaddr@c {
  246. reg = <0xc 0x6>;
  247. };
  248. };
  249. partition11@1b0000 {
  250. compatible = "denx,fit";
  251. label = "firmware";
  252. reg = <0x001b0000 0x00e10000>;
  253. };
  254. partition12@fc0000 {
  255. label = "language";
  256. reg = <0x00fc0000 0x00040000>;
  257. read-only;
  258. };
  259. };
  260. };
  261. };
  262. &blsp1_uart1 {
  263. pinctrl-0 = <&serial_pins>;
  264. pinctrl-names = "default";
  265. status = "okay";
  266. };
  267. &blsp_dma {
  268. status = "okay";
  269. };
  270. &cryptobam {
  271. status = "okay";
  272. };
  273. &wifi0 {
  274. status = "okay";
  275. nvmem-cell-names = "pre-calibration", "mac-address";
  276. nvmem-cells = <&precal_art_1000>, <&macaddr_dnidata_0>;
  277. };
  278. &wifi1 {
  279. status = "okay";
  280. nvmem-cell-names = "pre-calibration", "mac-address";
  281. nvmem-cells = <&precal_art_5000>, <&macaddr_dnidata_c>;
  282. };