qcom-ipq4019-habanero-dvk.dts 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. /* Copyright (c) 2019, Robert Marko <[email protected]> */
  3. #include "qcom-ipq4019.dtsi"
  4. #include <dt-bindings/gpio/gpio.h>
  5. #include <dt-bindings/input/input.h>
  6. #include <dt-bindings/soc/qcom,tcsr.h>
  7. / {
  8. model = "8devices Habanero DVK";
  9. compatible = "8dev,habanero-dvk";
  10. aliases {
  11. led-boot = &led_status;
  12. led-failsafe = &led_status;
  13. led-running = &led_status;
  14. led-upgrade = &led_upgrade;
  15. };
  16. soc {
  17. rng@22000 {
  18. status = "okay";
  19. };
  20. mdio@90000 {
  21. status = "okay";
  22. pinctrl-0 = <&mdio_pins>;
  23. pinctrl-names = "default";
  24. };
  25. ess-psgmii@98000 {
  26. status = "okay";
  27. };
  28. counter@4a1000 {
  29. compatible = "qcom,qca-gcnt";
  30. reg = <0x4a1000 0x4>;
  31. };
  32. tcsr@1949000 {
  33. compatible = "qcom,tcsr";
  34. reg = <0x1949000 0x100>;
  35. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  36. };
  37. tcsr@194b000 {
  38. status = "okay";
  39. compatible = "qcom,tcsr";
  40. reg = <0x194b000 0x100>;
  41. qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  42. };
  43. ess_tcsr@1953000 {
  44. compatible = "qcom,tcsr";
  45. reg = <0x1953000 0x1000>;
  46. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  47. };
  48. tcsr@1957000 {
  49. compatible = "qcom,tcsr";
  50. reg = <0x1957000 0x100>;
  51. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  52. };
  53. usb2: usb2@60f8800 {
  54. status = "okay";
  55. };
  56. usb3: usb3@8af8800 {
  57. status = "okay";
  58. };
  59. crypto@8e3a000 {
  60. status = "okay";
  61. };
  62. watchdog@b017000 {
  63. status = "okay";
  64. };
  65. ess-switch@c000000 {
  66. status = "okay";
  67. };
  68. edma@c080000 {
  69. status = "okay";
  70. };
  71. };
  72. keys {
  73. compatible = "gpio-keys";
  74. reset {
  75. label = "reset";
  76. gpios = <&tlmm 8 GPIO_ACTIVE_LOW>;
  77. linux,code = <KEY_RESTART>;
  78. };
  79. };
  80. leds {
  81. compatible = "gpio-leds";
  82. led_status: status {
  83. label = "green:status";
  84. gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
  85. panic-indicator;
  86. };
  87. led_upgrade: upgrade {
  88. label = "green:upgrade";
  89. gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
  90. };
  91. wlan2g {
  92. label = "green:wlan2g";
  93. gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
  94. linux,default-trigger = "phy0tpt";
  95. };
  96. wlan5g {
  97. label = "green:wlan5g";
  98. gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
  99. linux,default-trigger = "phy1tpt";
  100. };
  101. };
  102. };
  103. &vqmmc {
  104. status = "okay";
  105. };
  106. &sdhci {
  107. status = "okay";
  108. pinctrl-0 = <&sd_pins>;
  109. pinctrl-names = "default";
  110. cd-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
  111. vqmmc-supply = <&vqmmc>;
  112. };
  113. &qpic_bam {
  114. status = "okay";
  115. };
  116. &tlmm {
  117. mdio_pins: mdio_pinmux {
  118. mux_1 {
  119. pins = "gpio6";
  120. function = "mdio";
  121. bias-pull-up;
  122. };
  123. mux_2 {
  124. pins = "gpio7";
  125. function = "mdc";
  126. bias-pull-up;
  127. };
  128. };
  129. serial_pins: serial_pinmux {
  130. mux {
  131. pins = "gpio16", "gpio17";
  132. function = "blsp_uart0";
  133. bias-disable;
  134. };
  135. };
  136. spi_0_pins: spi_0_pinmux {
  137. pinmux {
  138. function = "blsp_spi0";
  139. pins = "gpio13", "gpio14", "gpio15";
  140. drive-strength = <12>;
  141. bias-disable;
  142. };
  143. pinmux_cs {
  144. function = "gpio";
  145. pins = "gpio12";
  146. drive-strength = <2>;
  147. bias-disable;
  148. output-high;
  149. };
  150. };
  151. nand_pins: nand_pins {
  152. pullups {
  153. pins = "gpio52", "gpio53", "gpio58", "gpio59";
  154. function = "qpic";
  155. bias-pull-up;
  156. };
  157. pulldowns {
  158. pins = "gpio54", "gpio55", "gpio56", "gpio57",
  159. "gpio60", "gpio62", "gpio63", "gpio64",
  160. "gpio65", "gpio66", "gpio67", "gpio68",
  161. "gpio69";
  162. function = "qpic";
  163. bias-pull-down;
  164. };
  165. };
  166. sd_pins: sd_pins {
  167. pinmux {
  168. function = "sdio";
  169. pins = "gpio23", "gpio24", "gpio25", "gpio26",
  170. "gpio28", "gpio29", "gpio30", "gpio31";
  171. drive-strength = <10>;
  172. };
  173. pinmux_sd_clk {
  174. function = "sdio";
  175. pins = "gpio27";
  176. drive-strength = <16>;
  177. };
  178. pinmux_sd7 {
  179. function = "sdio";
  180. pins = "gpio32";
  181. drive-strength = <10>;
  182. bias-disable;
  183. };
  184. };
  185. };
  186. &blsp_dma {
  187. status = "okay";
  188. };
  189. &blsp1_spi1 {
  190. status = "okay";
  191. pinctrl-0 = <&spi_0_pins>;
  192. pinctrl-names = "default";
  193. cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
  194. flash@0 {
  195. compatible = "jedec,spi-nor";
  196. spi-max-frequency = <24000000>;
  197. reg = <0>;
  198. partitions {
  199. compatible = "fixed-partitions";
  200. #address-cells = <1>;
  201. #size-cells = <1>;
  202. partition@0 {
  203. label = "SBL1";
  204. reg = <0x00000000 0x00040000>;
  205. read-only;
  206. };
  207. partition@40000 {
  208. label = "MIBIB";
  209. reg = <0x00040000 0x00020000>;
  210. read-only;
  211. };
  212. partition@60000 {
  213. label = "QSEE";
  214. reg = <0x00060000 0x00060000>;
  215. read-only;
  216. };
  217. partition@c0000 {
  218. label = "CDT";
  219. reg = <0x000c0000 0x00010000>;
  220. read-only;
  221. };
  222. partition@d0000 {
  223. label = "DDRPARAMS";
  224. reg = <0x000d0000 0x00010000>;
  225. read-only;
  226. };
  227. partition@e0000 {
  228. label = "APPSBLENV"; /* uboot env */
  229. reg = <0x000e0000 0x00010000>;
  230. read-only;
  231. };
  232. partition@f0000 {
  233. label = "APPSBL"; /* uboot */
  234. reg = <0x000f0000 0x00080000>;
  235. read-only;
  236. };
  237. partition@170000 {
  238. label = "ART";
  239. reg = <0x00170000 0x00010000>;
  240. read-only;
  241. };
  242. partition@180000 {
  243. label = "cfg";
  244. reg = <0x00180000 0x00040000>;
  245. };
  246. partition@1c0000 {
  247. label = "firmware";
  248. compatible = "denx,fit";
  249. reg = <0x001c0000 0x01e40000>;
  250. };
  251. };
  252. };
  253. };
  254. /* Some DVK boards ship without NAND */
  255. &nand {
  256. status = "okay";
  257. pinctrl-0 = <&nand_pins>;
  258. pinctrl-names = "default";
  259. };
  260. &blsp1_uart1 {
  261. status = "okay";
  262. pinctrl-0 = <&serial_pins>;
  263. pinctrl-names = "default";
  264. };
  265. &cryptobam {
  266. status = "okay";
  267. };
  268. &pcie0 {
  269. status = "okay";
  270. perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
  271. wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
  272. /* Free slot for use */
  273. bridge@0,0 {
  274. reg = <0x00000000 0 0 0 0>;
  275. #address-cells = <3>;
  276. #size-cells = <2>;
  277. ranges;
  278. };
  279. };
  280. &wifi0 {
  281. status = "okay";
  282. qcom,ath10k-calibration-variant = "8devices-Habanero";
  283. };
  284. &wifi1 {
  285. status = "okay";
  286. qcom,ath10k-calibration-variant = "8devices-Habanero";
  287. };
  288. &usb3_ss_phy {
  289. status = "okay";
  290. };
  291. &usb3_hs_phy {
  292. status = "okay";
  293. };
  294. &usb2_hs_phy {
  295. status = "okay";
  296. };