qcom-ipq4019-r619ac.dtsi 5.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "qcom-ipq4019.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. #include <dt-bindings/soc/qcom,tcsr.h>
  6. #include <dt-bindings/leds/common.h>
  7. / {
  8. chosen {
  9. bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
  10. };
  11. aliases {
  12. led-boot = &led_sys;
  13. led-failsafe = &led_sys;
  14. led-running = &led_sys;
  15. led-upgrade = &led_sys;
  16. label-mac-device = &gmac0;
  17. };
  18. soc {
  19. rng@22000 {
  20. status = "okay";
  21. };
  22. mdio@90000 {
  23. status = "okay";
  24. pinctrl-0 = <&mdio_pins>;
  25. pinctrl-names = "default";
  26. };
  27. ess-psgmii@98000 {
  28. status = "okay";
  29. };
  30. tcsr@1949000 {
  31. compatible = "qcom,tcsr";
  32. reg = <0x1949000 0x100>;
  33. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  34. };
  35. tcsr@194b000 {
  36. compatible = "qcom,tcsr";
  37. reg = <0x194b000 0x100>;
  38. qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  39. };
  40. ess_tcsr@1953000 {
  41. compatible = "qcom,tcsr";
  42. reg = <0x1953000 0x1000>;
  43. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  44. };
  45. tcsr@1957000 {
  46. compatible = "qcom,tcsr";
  47. reg = <0x1957000 0x100>;
  48. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  49. };
  50. usb2@60f8800 {
  51. status = "okay";
  52. };
  53. usb3@8af8800 {
  54. status = "okay";
  55. };
  56. crypto@8e3a000 {
  57. status = "okay";
  58. };
  59. watchdog@b017000 {
  60. status = "okay";
  61. };
  62. ess-switch@c000000 {
  63. status = "okay";
  64. };
  65. edma@c080000 {
  66. status = "okay";
  67. };
  68. };
  69. leds {
  70. compatible = "gpio-leds";
  71. led_sys: led-0 {
  72. label = "blue:sys";
  73. gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;
  74. color = <LED_COLOR_ID_BLUE>;
  75. function = LED_FUNCTION_POWER;
  76. };
  77. led-1 {
  78. label = "blue:wlan2g";
  79. gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
  80. linux,default-trigger = "phy0tpt";
  81. color = <LED_COLOR_ID_BLUE>;
  82. function = LED_FUNCTION_WLAN;
  83. function-enumerator = <0>;
  84. };
  85. led-2 {
  86. label = "blue:wlan5g";
  87. gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
  88. linux,default-trigger = "phy1tpt";
  89. color = <LED_COLOR_ID_BLUE>;
  90. function = LED_FUNCTION_WLAN;
  91. function-enumerator = <1>;
  92. };
  93. };
  94. keys {
  95. compatible = "gpio-keys";
  96. reset {
  97. label = "reset";
  98. gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
  99. linux,code = <KEY_RESTART>;
  100. };
  101. };
  102. };
  103. &blsp_dma {
  104. status = "okay";
  105. };
  106. &blsp1_spi1 {
  107. status = "okay";
  108. flash@0 {
  109. reg = <0>;
  110. compatible = "jedec,spi-nor";
  111. spi-max-frequency = <24000000>;
  112. partitions {
  113. compatible = "fixed-partitions";
  114. #address-cells = <1>;
  115. #size-cells = <1>;
  116. partition@0 {
  117. label = "SBL1";
  118. reg = <0x0 0x40000>;
  119. read-only;
  120. };
  121. partition@40000 {
  122. label = "MIBIB";
  123. reg = <0x40000 0x20000>;
  124. read-only;
  125. };
  126. partition@60000 {
  127. label = "QSEE";
  128. reg = <0x60000 0x60000>;
  129. read-only;
  130. };
  131. partition@c0000 {
  132. label = "CDT";
  133. reg = <0xc0000 0x10000>;
  134. read-only;
  135. };
  136. partition@d0000 {
  137. label = "DDRPARAMS";
  138. reg = <0xd0000 0x10000>;
  139. read-only;
  140. };
  141. partition@e0000 {
  142. label = "APPSBLENV";
  143. reg = <0xe0000 0x10000>;
  144. read-only;
  145. };
  146. partition@f0000 {
  147. label = "APPSBL";
  148. reg = <0xf0000 0x80000>;
  149. read-only;
  150. };
  151. partition@170000 {
  152. label = "ART";
  153. reg = <0x170000 0x10000>;
  154. read-only;
  155. };
  156. };
  157. };
  158. };
  159. &nand {
  160. status = "okay";
  161. nand@0 {
  162. partitions {
  163. compatible = "fixed-partitions";
  164. #address-cells = <1>;
  165. #size-cells = <1>;
  166. nand_rootfs: partition@0 {
  167. label = "ubi";
  168. /* reg defined in 64M/128M variant dts. */
  169. };
  170. };
  171. };
  172. };
  173. &blsp1_uart1 {
  174. pinctrl-0 = <&serial_0_pins>;
  175. pinctrl-names = "default";
  176. status = "okay";
  177. };
  178. &cryptobam {
  179. status = "okay";
  180. };
  181. &pcie0 {
  182. status = "okay";
  183. pinctrl-names = "default";
  184. pinctrl-0 = <&pcie_pins>;
  185. perst-gpio = <&tlmm 4 GPIO_ACTIVE_LOW>;
  186. wake-gpio = <&tlmm 40 GPIO_ACTIVE_HIGH>;
  187. /* Free slot for use */
  188. bridge@0,0 {
  189. reg = <0x00000000 0 0 0 0>;
  190. #address-cells = <3>;
  191. #size-cells = <2>;
  192. ranges;
  193. };
  194. };
  195. &qpic_bam {
  196. status = "okay";
  197. };
  198. &sdhci {
  199. pinctrl-0 = <&sd_0_pins>;
  200. pinctrl-names = "default";
  201. vqmmc-supply = <&vqmmc>;
  202. status = "okay";
  203. };
  204. &tlmm {
  205. pcie_pins: pcie_pinmux {
  206. mux {
  207. pins = "gpio2";
  208. function = "gpio";
  209. output-low;
  210. bias-pull-down;
  211. };
  212. };
  213. mdio_pins: mdio_pinmux {
  214. mux_1 {
  215. pins = "gpio6";
  216. function = "mdio";
  217. bias-pull-up;
  218. };
  219. mux_2 {
  220. pins = "gpio7";
  221. function = "mdc";
  222. bias-pull-up;
  223. };
  224. };
  225. sd_0_pins: sd_0_pinmux {
  226. mux_1 {
  227. pins = "gpio23", "gpio24", "gpio25", "gpio26", "gpio28";
  228. function = "sdio";
  229. drive-strength = <10>;
  230. };
  231. mux_2 {
  232. pins = "gpio27";
  233. function = "sdio";
  234. drive-strength = <16>;
  235. };
  236. };
  237. serial_0_pins: serial0-pinmux {
  238. mux {
  239. pins = "gpio16", "gpio17";
  240. function = "blsp_uart0";
  241. bias-disable;
  242. };
  243. };
  244. };
  245. &ethphy0 {
  246. qcom,single-led-1000;
  247. qcom,single-led-100;
  248. qcom,single-led-10;
  249. };
  250. &ethphy1 {
  251. qcom,single-led-1000;
  252. qcom,single-led-100;
  253. qcom,single-led-10;
  254. };
  255. &ethphy2 {
  256. qcom,single-led-1000;
  257. qcom,single-led-100;
  258. qcom,single-led-10;
  259. };
  260. &ethphy3 {
  261. qcom,single-led-1000;
  262. qcom,single-led-100;
  263. qcom,single-led-10;
  264. };
  265. &ethphy4 {
  266. qcom,single-led-1000;
  267. qcom,single-led-100;
  268. qcom,single-led-10;
  269. };
  270. &usb3_ss_phy {
  271. status = "okay";
  272. };
  273. &usb3_hs_phy {
  274. status = "okay";
  275. };
  276. &usb2_hs_phy {
  277. status = "okay";
  278. };
  279. &vqmmc {
  280. status = "okay";
  281. };
  282. &wifi0 {
  283. status = "okay";
  284. qcom,ath10k-calibration-variant = "P&W R619AC";
  285. };
  286. &wifi1 {
  287. status = "okay";
  288. qcom,ath10k-calibration-variant = "P&W R619AC";
  289. };