qcom-ipq4019-u4019-32m.dts 1.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "qcom-ipq4019-u4019.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. / {
  6. model = "Unielec U4019 (32M)";
  7. compatible = "unielec,u4019-32m","unielec,u4019","qcom,ipq4019";
  8. };
  9. &blsp1_spi1 {
  10. pinctrl-0 = <&spi_0_pins>;
  11. pinctrl-names = "default";
  12. status = "okay";
  13. cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
  14. flash@0 {
  15. reg = <0>;
  16. compatible = "jedec,spi-nor";
  17. spi-max-frequency = <24000000>;
  18. broken-flash-reset;
  19. partitions {
  20. compatible = "fixed-partitions";
  21. #address-cells = <1>;
  22. #size-cells = <1>;
  23. partition@0 {
  24. label = "0:SBL1";
  25. reg = <0x0 0x40000>;
  26. read-only;
  27. };
  28. partition@40000 {
  29. label = "0:MIBIB";
  30. reg = <0x40000 0x20000>;
  31. read-only;
  32. };
  33. partition@60000 {
  34. label = "0:QSEE";
  35. reg = <0x60000 0x60000>;
  36. read-only;
  37. };
  38. partition@c0000 {
  39. label = "0:CDT";
  40. reg = <0xc0000 0x10000>;
  41. read-only;
  42. };
  43. partition@d0000 {
  44. label = "0:DDRPARAMS";
  45. reg = <0xd0000 0x10000>;
  46. read-only;
  47. };
  48. partition@e0000 {
  49. label = "0:APPSBLENV";
  50. reg = <0xe0000 0x10000>;
  51. read-only;
  52. };
  53. partition@f0000 {
  54. label = "0:APPSBL";
  55. reg = <0xf0000 0x80000>;
  56. read-only;
  57. };
  58. partition@170000 {
  59. label = "0:ART";
  60. reg = <0x170000 0x10000>;
  61. read-only;
  62. };
  63. partition@180000 {
  64. compatible = "denx,fit";
  65. label = "firmware";
  66. reg = <0x180000 0x1e80000>;
  67. };
  68. };
  69. };
  70. };