CS-QR10.dts 2.0 KB

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  1. /dts-v1/;
  2. #include "mt7620a.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. / {
  6. compatible = "planex,cs-qr10", "ralink,mt7620a-soc";
  7. model = "Planex CS-QR10";
  8. gpio-leds {
  9. compatible = "gpio-leds";
  10. power {
  11. label = "cs-qr10:red:power";
  12. gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
  13. };
  14. };
  15. gpio-keys-polled {
  16. compatible = "gpio-keys-polled";
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. poll-interval = <20>;
  20. s1 {
  21. label = "reset";
  22. gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
  23. linux,code = <KEY_RESTART>;
  24. };
  25. s2 {
  26. label = "wps";
  27. gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
  28. linux,code = <KEY_WPS_BUTTON>;
  29. };
  30. };
  31. };
  32. &gpio0 {
  33. status = "okay";
  34. };
  35. &gpio1 {
  36. status = "okay";
  37. };
  38. &gpio2 {
  39. status = "okay";
  40. };
  41. &gpio3 {
  42. status = "okay";
  43. };
  44. &i2c {
  45. status = "okay";
  46. };
  47. &i2s {
  48. status = "okay";
  49. pinctrl-names = "default";
  50. pinctrl-0 = <&pcm_i2s_pins>;
  51. };
  52. &spi0 {
  53. status = "okay";
  54. m25p80@0 {
  55. #address-cells = <1>;
  56. #size-cells = <1>;
  57. compatible = "jedec,spi-nor";
  58. reg = <0>;
  59. spi-max-frequency = <10000000>;
  60. partition@0 {
  61. label = "u-boot";
  62. reg = <0x0 0x30000>;
  63. read-only;
  64. };
  65. partition@30000 {
  66. label = "u-boot-env";
  67. reg = <0x30000 0x10000>;
  68. read-only;
  69. };
  70. factory: partition@40000 {
  71. label = "factory";
  72. reg = <0x40000 0x10000>;
  73. read-only;
  74. };
  75. partition@50000 {
  76. label = "firmware";
  77. reg = <0x50000 0x7b0000>;
  78. };
  79. };
  80. };
  81. &pcm {
  82. status = "okay";
  83. };
  84. &gdma {
  85. status = "okay";
  86. };
  87. &pinctrl {
  88. state_default: pinctrl0 {
  89. gpio {
  90. ralink,group = "spi refclk", "rgmii1";
  91. ralink,function = "gpio";
  92. };
  93. wdt {
  94. ralink,group = "wdt";
  95. ralink,function = "wdt refclk";
  96. };
  97. };
  98. };
  99. &ethernet {
  100. pinctrl-names = "default";
  101. pinctrl-0 = <&ephy_pins>;
  102. mtd-mac-address = <&factory 0x4>;
  103. mediatek,portmap = "llllw";
  104. };
  105. &gsw {
  106. ralink,port4 = "ephy";
  107. };
  108. &sdhci {
  109. status = "okay";
  110. };
  111. &ehci {
  112. status = "okay";
  113. };
  114. &ohci {
  115. status = "okay";
  116. };
  117. &wmac {
  118. ralink,mtd-eeprom = <&factory 0>;
  119. };
  120. &pcie {
  121. status = "okay";
  122. };