MZK-WDPR.dts 1.3 KB

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  1. /dts-v1/;
  2. #include "rt3050.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. / {
  5. compatible = "planex,mzk-wdpr", "ralink,rt3052-soc";
  6. model = "Planex MZK-WDPR";
  7. chosen {
  8. bootargs = "console=ttyS0,115200";
  9. };
  10. cfi@1f000000 {
  11. compatible = "cfi-flash";
  12. reg = <0x1f000000 0x800000>;
  13. bank-width = <2>;
  14. device-width = <2>;
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. partition@0 {
  18. label = "u-boot";
  19. reg = <0x0 0x30000>;
  20. read-only;
  21. };
  22. partition@30000 {
  23. label = "u-boot-env";
  24. reg = <0x30000 0x10000>;
  25. read-only;
  26. };
  27. factory: partition@40000 {
  28. label = "factory";
  29. reg = <0x40000 0x10000>;
  30. read-only;
  31. };
  32. partition@7f0000 {
  33. label = "Data3G";
  34. reg = <0x7f0000 0x10000>;
  35. read-only;
  36. };
  37. partition@50000 {
  38. label = "firmware";
  39. reg = <0x50000 0x680000>;
  40. };
  41. };
  42. gpio-export {
  43. compatible = "gpio-export";
  44. lcd_ctrl1 {
  45. gpio-export,name = "lcd_ctrl1";
  46. gpio-export,output = <0>;
  47. gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
  48. };
  49. };
  50. };
  51. &pinctrl {
  52. state_default: pinctrl0 {
  53. gpio {
  54. ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf";
  55. ralink,function = "gpio";
  56. };
  57. };
  58. };
  59. &ethernet {
  60. mtd-mac-address = <&factory 0x28>;
  61. };
  62. &esw {
  63. mediatek,portmap = <0x2f>;
  64. };
  65. &wmac {
  66. ralink,mtd-eeprom = <&factory 0>;
  67. };
  68. &otg {
  69. status = "okay";
  70. };