RE6500.dts 2.0 KB

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  1. /dts-v1/;
  2. #include "mt7621.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. / {
  6. compatible = "linksys,re6500", "mediatek,mt7621-soc";
  7. model = "Linksys RE6500";
  8. memory@0 {
  9. device_type = "memory";
  10. reg = <0x0 0x4000000>;
  11. };
  12. chosen {
  13. bootargs = "console=ttyS0,57600";
  14. };
  15. gpio-leds {
  16. compatible = "gpio-leds";
  17. wifi {
  18. label = "re6500:orange:wifi";
  19. gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
  20. };
  21. power {
  22. label = "re6500:white:power";
  23. gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
  24. };
  25. };
  26. gpio-keys-polled {
  27. compatible = "gpio-keys-polled";
  28. #address-cells = <1>;
  29. #size-cells = <0>;
  30. poll-interval = <20>;
  31. wps {
  32. label = "wps";
  33. gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
  34. linux,code = <KEY_WPS_BUTTON>;
  35. };
  36. reset {
  37. label = "reset";
  38. gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
  39. linux,code = <KEY_RESTART>;
  40. };
  41. };
  42. };
  43. &spi0 {
  44. status = "okay";
  45. m25p80@0 {
  46. #address-cells = <1>;
  47. #size-cells = <1>;
  48. compatible = "jedec,spi-nor";
  49. reg = <0>;
  50. spi-max-frequency = <10000000>;
  51. m25p,chunked-io = <32>;
  52. partition@0 {
  53. label = "u-boot";
  54. reg = <0x0 0x30000>;
  55. read-only;
  56. };
  57. partition@30000 {
  58. label = "u-boot-env";
  59. reg = <0x30000 0x10000>;
  60. read-only;
  61. };
  62. factory: partition@40000 {
  63. label = "factory";
  64. reg = <0x40000 0x10000>;
  65. read-only;
  66. };
  67. partition@50000 {
  68. label = "firmware";
  69. reg = <0x50000 0x7b0000>;
  70. };
  71. };
  72. };
  73. &pinctrl {
  74. state_default: pinctrl0 {
  75. gpio {
  76. ralink,group = "i2c", "uart2", "uart3", "rgmii2";
  77. ralink,function = "gpio";
  78. };
  79. };
  80. };
  81. &pcie {
  82. status = "okay";
  83. pcie0 {
  84. mt76@0,0 {
  85. reg = <0x0000 0 0 0 0>;
  86. device_type = "pci";
  87. mediatek,mtd-eeprom = <&factory 0x0000>;
  88. ieee80211-freq-limit = <5000000 6000000>;
  89. };
  90. };
  91. pcie1 {
  92. mt76@1,0 {
  93. reg = <0x0000 0 0 0 0>;
  94. device_type = "pci";
  95. mediatek,mtd-eeprom = <&factory 0x8000>;
  96. ieee80211-freq-limit = <2400000 2500000>;
  97. };
  98. };
  99. };
  100. &ethernet {
  101. mtd-mac-address = <&factory 0x2e>;
  102. };
  103. &xhci {
  104. status = "disabled";
  105. };