WL-351.dts 2.2 KB

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  1. /dts-v1/;
  2. #include "rt3050.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. / {
  6. compatible = "sitecom,wl-351", "ralink,rt3052-soc";
  7. model = "Sitecom WL-351 v1 002";
  8. cfi@1f000000 {
  9. compatible = "cfi-flash";
  10. reg = <0x1f000000 0x800000>;
  11. bank-width = <2>;
  12. device-width = <2>;
  13. #address-cells = <1>;
  14. #size-cells = <1>;
  15. partition@0 {
  16. label = "u-boot";
  17. reg = <0x0 0x30000>;
  18. read-only;
  19. };
  20. partition@30000 {
  21. label = "u-boot-env";
  22. reg = <0x30000 0x10000>;
  23. read-only;
  24. };
  25. factory: partition@40000 {
  26. label = "factory";
  27. reg = <0x40000 0x10000>;
  28. read-only;
  29. };
  30. partition@50000 {
  31. label = "firmware";
  32. reg = <0x50000 0x3b0000>;
  33. };
  34. };
  35. gpio-leds {
  36. compatible = "gpio-leds";
  37. power {
  38. label = "wl-351:amber:power";
  39. gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
  40. };
  41. unpopulated {
  42. label = "wl-351:amber:unpopulated";
  43. gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
  44. };
  45. unpopulated2 {
  46. label = "wl-351:blue:unpopulated";
  47. gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
  48. };
  49. };
  50. gpio-keys-polled {
  51. compatible = "gpio-keys-polled";
  52. #address-cells = <1>;
  53. #size-cells = <0>;
  54. poll-interval = <20>;
  55. reset {
  56. label = "reset";
  57. gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
  58. linux,code = <KEY_RESTART>;
  59. };
  60. wps {
  61. label = "wps";
  62. gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
  63. linux,code = <KEY_WPS_BUTTON>;
  64. };
  65. };
  66. rtl8366rb {
  67. compatible = "realtek,rtl8366rb";
  68. gpio-sda = <&gpio0 1 GPIO_ACTIVE_HIGH>;
  69. gpio-sck = <&gpio0 2 GPIO_ACTIVE_HIGH>;
  70. };
  71. };
  72. &pinctrl {
  73. state_default: pinctrl0 {
  74. gpio {
  75. ralink,group = "spi", "i2c", "jtag", "mdio", "uartf";
  76. ralink,function = "gpio";
  77. };
  78. };
  79. };
  80. &ethernet {
  81. mtd-mac-address = <&factory 0x4>;
  82. pinctrl-names = "default";
  83. pinctrl-0 = <&rgmii_pins>;
  84. };
  85. &esw {
  86. ralink,rgmii = <1>;
  87. mediatek,portmap = <0x3f>;
  88. ralink,fct2 = <0x0002500c>;
  89. /*
  90. * ext phy base addr 31, rx/tx clock skew 0,
  91. * turbo mii off, rgmi 3.3v off, port 5 polling off
  92. * port5: enabled, gige, full-duplex, rx/tx-flow-control
  93. * port6: enabled, gige, full-duplex, rx/tx-flow-control
  94. */
  95. ralink,fpa2 = <0x1f003fff>;
  96. };
  97. &wmac {
  98. ralink,mtd-eeprom = <&factory 0>;
  99. };
  100. &otg {
  101. status = "okay";
  102. };