bcm6345.dtsi 1.7 KB

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  1. /dts-v1/;
  2. / {
  3. #address-cells = <1>;
  4. #size-cells = <1>;
  5. compatible = "brcm,bcm6345";
  6. aliases {
  7. pflash = &pflash;
  8. serial0 = &uart0;
  9. gpio0 = &gpio0;
  10. };
  11. cpus {
  12. #address-cells = <1>;
  13. #size-cells = <0>;
  14. cpu@0 {
  15. compatible = "brcm,bmips32", "mips,mips4Kc";
  16. device_type = "cpu";
  17. reg = <0>;
  18. };
  19. };
  20. cpu_intc: interrupt-controller {
  21. #address-cells = <0>;
  22. compatible = "mti,cpu-interrupt-controller";
  23. interrupt-controller;
  24. #interrupt-cells = <1>;
  25. };
  26. memory { device_type = "memory"; reg = <0 0>; };
  27. pflash: nor@1fc00000 {
  28. compatible = "cfi-flash";
  29. reg = <0x1fc00000 0x400000>;
  30. bank-width = <2>;
  31. #address-cells = <1>;
  32. #size-cells = <1>;
  33. status = "disabled";
  34. };
  35. ubus@fff00000 {
  36. #address-cells = <1>;
  37. #size-cells = <1>;
  38. ranges;
  39. compatible = "simple-bus";
  40. periph_intc: interrupt-controller@fffe000c {
  41. compatible = "brcm,bcm6345-l1-intc";
  42. reg = <0xfffe000c 0x9>;
  43. interrupt-controller;
  44. #interrupt-cells = <1>;
  45. interrupt-parent = <&cpu_intc>;
  46. interrupts = <2>;
  47. };
  48. ext_intc: interrupt-controller@fffe0014 {
  49. compatible = "brcm,bcm6345-ext-intc";
  50. reg = <0xfffe0014 0x4>;
  51. interrupt-controller;
  52. #interrupt-cells = <2>;
  53. interrupt-parent = <&cpu_intc>;
  54. interrupts = <3>, <4>, <5>, <6>;
  55. };
  56. uart0: serial@fffe0300 {
  57. compatible = "brcm,bcm6345-uart";
  58. reg = <0xfffe0300 0x18>;
  59. interrupt-parent = <&periph_intc>;
  60. interrupts = <2>;
  61. /* clocks = <&periph_clk>; */
  62. /* clock-names = "refclk"; */
  63. status = "disabled";
  64. };
  65. gpio0: gpio-controller@fffe0404 {
  66. compatible = "brcm,bcm6345-gpio";
  67. reg = <0xfffe0404 4>, <0xfffe0408 4>;
  68. gpio-controller;
  69. #gpio-cells = <2>;
  70. ngpios = <16>;
  71. };
  72. };
  73. };