bcm6348.dtsi 2.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155
  1. /dts-v1/;
  2. / {
  3. #address-cells = <1>;
  4. #size-cells = <1>;
  5. compatible = "brcm,bcm6348";
  6. aliases {
  7. pflash = &pflash;
  8. pinctrl = &pinctrl;
  9. serial0 = &uart0;
  10. spi0 = &lsspi;
  11. };
  12. cpus {
  13. #address-cells = <1>;
  14. #size-cells = <0>;
  15. cpu@0 {
  16. compatible = "brcm,bmips3300", "mips,mips4Kc";
  17. device_type = "cpu";
  18. reg = <0>;
  19. };
  20. };
  21. cpu_intc: interrupt-controller {
  22. #address-cells = <0>;
  23. compatible = "mti,cpu-interrupt-controller";
  24. interrupt-controller;
  25. #interrupt-cells = <1>;
  26. };
  27. memory { device_type = "memory"; reg = <0 0>; };
  28. pflash: nor@1fc00000 {
  29. compatible = "cfi-flash";
  30. reg = <0x1fc00000 0x400000>;
  31. bank-width = <2>;
  32. #address-cells = <1>;
  33. #size-cells = <1>;
  34. status = "disabled";
  35. };
  36. ubus@fff00000 {
  37. #address-cells = <1>;
  38. #size-cells = <1>;
  39. ranges;
  40. compatible = "simple-bus";
  41. interrupt-parent = <&periph_intc>;
  42. periph_intc: interrupt-controller@fffe000c {
  43. compatible = "brcm,bcm6345-l1-intc";
  44. reg = <0xfffe000c 0x8>;
  45. interrupt-controller;
  46. #interrupt-cells = <1>;
  47. interrupt-parent = <&cpu_intc>;
  48. interrupts = <2>;
  49. };
  50. ext_intc: interrupt-controller@fffe0014 {
  51. compatible = "brcm,bcm6345-ext-intc";
  52. reg = <0xfffe0014 0x4>;
  53. interrupt-controller;
  54. #interrupt-cells = <2>;
  55. interrupt-parent = <&cpu_intc>;
  56. interrupts = <3>, <4>, <5>, <6>;
  57. brcm,field-width = <5>;
  58. };
  59. pinctrl: pin-controller@fffe0400 {
  60. compatible = "brcm,bcm6348-pinctrl";
  61. reg = <0xfffe0400 0x8>,
  62. <0xfffe0408 0x8>,
  63. <0xfffe0418 0x4>;
  64. reg-names = "dirout", "dat", "mode";
  65. gpio-controller;
  66. #gpio-cells = <2>;
  67. interrupt-parent = <&ext_intc>;
  68. interrupts = <0 0>, <1 0>, <2 0>, <3 0>;
  69. interrupt-names = "gpio32", "gpio33", "gpio34", "gpio35";
  70. pinctrl_ext_ephy: ext_ephy {
  71. function = "ext_ephy";
  72. groups = "group1", "group4";
  73. };
  74. pinctrl_mii_snoop: mii_snoop {
  75. function = "ext_ephy";
  76. groups = "group1", "group4";
  77. };
  78. pinctrl_legacy_led: legacy_led {
  79. function = "legacy_led";
  80. groups = "group4";
  81. };
  82. pinctrl_mii_pccard: mii_pccard {
  83. function = "mii_pccard";
  84. groups = "group1";
  85. };
  86. pinctrl_pci: pci {
  87. function = "pci";
  88. groups = "group2";
  89. };
  90. pinctrl_spi_master_uart: spi_master_uart {
  91. function = "spi_master_uart";
  92. groups = "group1";
  93. };
  94. pinctrl_ext_mii: ext_mii {
  95. function = "ext_mii";
  96. groups = "group0", "group3";
  97. };
  98. pinctrl_utopia: utopia {
  99. function = "utopia";
  100. groups = "group0", "group1", "group3";
  101. };
  102. };
  103. uart0: serial@fffe0300 {
  104. compatible = "brcm,bcm6345-uart";
  105. reg = <0xfffe0300 0x18>;
  106. interrupt-parent = <&periph_intc>;
  107. interrupts = <2>;
  108. /* clocks = <&periph_clk>; */
  109. /* clock-names = "refclk"; */
  110. status = "disabled";
  111. };
  112. lsspi: spi@fffe0c00 {
  113. #address-cells = <1>;
  114. #size-cells = <0>;
  115. compatible = "brcm,bcm6348-spi";
  116. reg = <0xfffe0c00 0x40>;
  117. interrupts = <1>;
  118. /* clocks = <&clkctl 9>; */
  119. };
  120. };
  121. };