rtl8380_engenius_ews2910p.dts 4.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. #include "rtl838x.dtsi"
  3. #include <dt-bindings/input/input.h>
  4. #include <dt-bindings/gpio/gpio.h>
  5. / {
  6. compatible = "engenius,ews2910p", "realtek,rtl838x-soc";
  7. model = "EnGenius EWS2910P";
  8. aliases {
  9. led-boot = &led_power;
  10. led-failsafe = &led_fault;
  11. led-running = &led_power;
  12. led-upgrade = &led_power;
  13. };
  14. memory@0 {
  15. device_type = "memory";
  16. reg = <0x0 0x10000000>;
  17. };
  18. keys {
  19. compatible = "gpio-keys";
  20. reset {
  21. label = "reset";
  22. gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
  23. linux,code = <KEY_RESTART>;
  24. };
  25. led_mode {
  26. label = "led-mode";
  27. gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
  28. linux,code = <BTN_0>;
  29. };
  30. };
  31. gpio1: rtl8231-gpio {
  32. compatible = "realtek,rtl8231-gpio";
  33. #gpio-cells = <2>;
  34. gpio-controller;
  35. indirect-access-bus-id = <0>;
  36. poe_enable {
  37. gpio-hog;
  38. gpios = <1 GPIO_ACTIVE_HIGH>;
  39. output-high;
  40. line-name = "poe-enable";
  41. };
  42. sff_p9_gpios {
  43. gpio-hog;
  44. gpios = < 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>,
  45. < 11 GPIO_ACTIVE_HIGH>, /* los-gpio */
  46. < 12 GPIO_ACTIVE_LOW>; /* mod-def0-gpio */
  47. input;
  48. line-name = "sff-p9-gpios";
  49. };
  50. };
  51. gpio-export {
  52. compatible = "gpio-export";
  53. sff-p9-tx-disable {
  54. gpio-export,name = "sff-p9-tx-disable";
  55. gpio-export,output = <1>;
  56. gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
  57. };
  58. };
  59. gpio-restart {
  60. compatible = "gpio-restart";
  61. gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
  62. };
  63. leds {
  64. compatible = "gpio-leds";
  65. led_power: led-0 {
  66. label = "green:power";
  67. gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
  68. };
  69. led_lan_mode: led-1 {
  70. label = "green:lan-mode";
  71. gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
  72. };
  73. led_fault: led-2 {
  74. label = "amber:fault";
  75. gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
  76. };
  77. led_poe_max: led-3 {
  78. label = "amber:poe-max";
  79. gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
  80. };
  81. };
  82. i2c1: i2c-gpio-1 {
  83. compatible = "i2c-gpio";
  84. sda-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  85. scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  86. i2c-gpio,delay-us = <2>;
  87. #address-cells = <1>;
  88. #size-cells = <0>;
  89. };
  90. sfp1: sfp-p10 {
  91. compatible = "sff,sfp";
  92. i2c-bus = <&i2c1>;
  93. tx-disable-gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
  94. los-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
  95. mod-def0-gpio = <&gpio1 21 GPIO_ACTIVE_LOW>;
  96. };
  97. };
  98. &spi0 {
  99. status = "okay";
  100. flash@0 {
  101. compatible = "jedec,spi-nor";
  102. reg = <0>;
  103. spi-max-frequency = <10000000>;
  104. partitions {
  105. compatible = "fixed-partitions";
  106. #address-cells = <1>;
  107. #size-cells = <1>;
  108. partition@0 {
  109. label = "u-boot";
  110. reg = <0x0 0x80000>;
  111. read-only;
  112. };
  113. partition@80000 {
  114. label = "u-boot-env";
  115. reg = <0x80000 0x10000>;
  116. read-only;
  117. };
  118. partition@90000 {
  119. label = "u-boot-env2";
  120. reg = <0x90000 0x10000>;
  121. };
  122. partition@a0000 {
  123. label = "rootfs_data";
  124. reg = <0xa0000 0xd60000>;
  125. };
  126. partition@e00000 {
  127. label = "jffs2-log";
  128. reg = <0xe00000 0x200000>;
  129. };
  130. partition@1000000 {
  131. compatible = "openwrt,uimage";
  132. label = "firmware";
  133. reg = <0x1000000 0x800000>;
  134. openwrt,ih-magic = <0x03802910>;
  135. };
  136. partition@1800000 {
  137. label = "firmware2";
  138. reg = <0x1800000 0x800000>;
  139. };
  140. };
  141. };
  142. };
  143. &ethernet0 {
  144. mdio: mdio-bus {
  145. compatible = "realtek,rtl838x-mdio";
  146. regmap = <&ethernet0>;
  147. #address-cells = <1>;
  148. #size-cells = <0>;
  149. INTERNAL_PHY(8)
  150. INTERNAL_PHY(9)
  151. INTERNAL_PHY(10)
  152. INTERNAL_PHY(11)
  153. INTERNAL_PHY(12)
  154. INTERNAL_PHY(13)
  155. INTERNAL_PHY(14)
  156. INTERNAL_PHY(15)
  157. INTERNAL_PHY(24)
  158. INTERNAL_PHY(26)
  159. };
  160. };
  161. &switch0 {
  162. ports {
  163. #address-cells = <1>;
  164. #size-cells = <0>;
  165. SWITCH_PORT(8, 1, internal)
  166. SWITCH_PORT(9, 2, internal)
  167. SWITCH_PORT(10, 3, internal)
  168. SWITCH_PORT(11, 4, internal)
  169. SWITCH_PORT(12, 5, internal)
  170. SWITCH_PORT(13, 6, internal)
  171. SWITCH_PORT(14, 7, internal)
  172. SWITCH_PORT(15, 8, internal)
  173. SWITCH_SFP_PORT(24, 9, 1000base-x)
  174. port@26 {
  175. reg = <26>;
  176. label = "lan10";
  177. phy-mode = "1000base-x";
  178. phy-handle = <&phy26>;
  179. managed = "in-band-status";
  180. sfp = <&sfp1>;
  181. };
  182. port@28 {
  183. ethernet = <&ethernet0>;
  184. reg = <28>;
  185. phy-mode = "internal";
  186. fixed-link {
  187. speed = <1000>;
  188. full-duplex;
  189. };
  190. };
  191. };
  192. };
  193. &uart1 {
  194. status = "okay";
  195. };