rtl8382_allnet_all-sg8208m.dts 2.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. #include "rtl838x.dtsi"
  3. #include <dt-bindings/input/input.h>
  4. #include <dt-bindings/gpio/gpio.h>
  5. / {
  6. compatible = "allnet,all-sg8208m", "realtek,rtl838x-soc";
  7. model = "ALLNET ALL-SG8208M";
  8. aliases {
  9. led-boot = &led_sys;
  10. led-failsafe = &led_sys;
  11. led-running = &led_sys;
  12. led-upgrade = &led_sys;
  13. };
  14. memory@0 {
  15. device_type = "memory";
  16. reg = <0x0 0x8000000>;
  17. };
  18. keys {
  19. compatible = "gpio-keys-polled";
  20. poll-interval = <20>;
  21. /* is this pin 3 on the external RTL8231 (&gpio1)? */
  22. /*reset {
  23. label = "reset";
  24. gpios = <&gpio0 67 GPIO_ACTIVE_LOW>;
  25. linux,code = <KEY_RESTART>;
  26. };*/
  27. };
  28. leds {
  29. pinctrl-names = "default";
  30. pinctrl-0 = <&pinmux_disable_sys_led>;
  31. compatible = "gpio-leds";
  32. led_sys: sys {
  33. label = "green:sys";
  34. gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
  35. };
  36. // GPIO 25: power on/off all port leds
  37. };
  38. };
  39. &spi0 {
  40. status = "okay";
  41. flash@0 {
  42. compatible = "jedec,spi-nor";
  43. reg = <0>;
  44. spi-max-frequency = <10000000>;
  45. partitions {
  46. compatible = "fixed-partitions";
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. partition@0 {
  50. label = "u-boot";
  51. reg = <0x0 0x80000>;
  52. read-only;
  53. };
  54. partition@80000 {
  55. label = "u-boot-env";
  56. reg = <0x80000 0x10000>;
  57. read-only;
  58. };
  59. partition@90000 {
  60. label = "u-boot-env2";
  61. reg = <0x90000 0x10000>;
  62. };
  63. partition@a0000 {
  64. label = "jffs";
  65. reg = <0xa0000 0x100000>;
  66. };
  67. partition@1a0000 {
  68. label = "jffs2";
  69. reg = <0x1a0000 0x100000>;
  70. };
  71. partition@2a0000 {
  72. label = "firmware";
  73. reg = <0x2a0000 0xd60000>;
  74. compatible = "openwrt,uimage", "denx,uimage";
  75. openwrt,ih-magic = <0x00000006>;
  76. };
  77. };
  78. };
  79. };
  80. &ethernet0 {
  81. mdio: mdio-bus {
  82. compatible = "realtek,rtl838x-mdio";
  83. regmap = <&ethernet0>;
  84. #address-cells = <1>;
  85. #size-cells = <0>;
  86. INTERNAL_PHY(8)
  87. INTERNAL_PHY(9)
  88. INTERNAL_PHY(10)
  89. INTERNAL_PHY(11)
  90. INTERNAL_PHY(12)
  91. INTERNAL_PHY(13)
  92. INTERNAL_PHY(14)
  93. INTERNAL_PHY(15)
  94. };
  95. };
  96. &switch0 {
  97. ports {
  98. #address-cells = <1>;
  99. #size-cells = <0>;
  100. SWITCH_PORT(8, 1, internal)
  101. SWITCH_PORT(9, 2, internal)
  102. SWITCH_PORT(10, 3, internal)
  103. SWITCH_PORT(11, 4, internal)
  104. SWITCH_PORT(12, 5, internal)
  105. SWITCH_PORT(13, 6, internal)
  106. SWITCH_PORT(14, 7, internal)
  107. SWITCH_PORT(15, 8, internal)
  108. port@28 {
  109. ethernet = <&ethernet0>;
  110. reg = <28>;
  111. phy-mode = "internal";
  112. fixed-link {
  113. speed = <1000>;
  114. full-duplex;
  115. };
  116. };
  117. };
  118. };