rtl8393_d-link_dgs-1210-52.dts 3.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163
  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "rtl839x.dtsi"
  3. #include "rtl83xx_d-link_dgs-1210_common.dtsi"
  4. #include "rtl83xx_d-link_dgs-1210_gpio.dtsi"
  5. #include "rtl839x_d-link_dgs-1210_gpio.dtsi"
  6. / {
  7. compatible = "d-link,dgs-1210-52", "realtek,rtl8393-soc";
  8. model = "D-Link DGS-1210-52";
  9. };
  10. &ethernet0 {
  11. mdio: mdio-bus {
  12. compatible = "realtek,rtl838x-mdio";
  13. regmap = <&ethernet0>;
  14. #address-cells = <1>;
  15. #size-cells = <0>;
  16. /* External phy RTL8218B #1 */
  17. EXTERNAL_PHY(0)
  18. EXTERNAL_PHY(1)
  19. EXTERNAL_PHY(2)
  20. EXTERNAL_PHY(3)
  21. EXTERNAL_PHY(4)
  22. EXTERNAL_PHY(5)
  23. EXTERNAL_PHY(6)
  24. EXTERNAL_PHY(7)
  25. /* External phy RTL8218B #2 */
  26. EXTERNAL_PHY(8)
  27. EXTERNAL_PHY(9)
  28. EXTERNAL_PHY(10)
  29. EXTERNAL_PHY(11)
  30. EXTERNAL_PHY(12)
  31. EXTERNAL_PHY(13)
  32. EXTERNAL_PHY(14)
  33. EXTERNAL_PHY(15)
  34. /* External phy RTL8218B #3 */
  35. EXTERNAL_PHY(16)
  36. EXTERNAL_PHY(17)
  37. EXTERNAL_PHY(18)
  38. EXTERNAL_PHY(19)
  39. EXTERNAL_PHY(20)
  40. EXTERNAL_PHY(21)
  41. EXTERNAL_PHY(22)
  42. EXTERNAL_PHY(23)
  43. /* External phy RTL8218B #4 */
  44. EXTERNAL_PHY(24)
  45. EXTERNAL_PHY(25)
  46. EXTERNAL_PHY(26)
  47. EXTERNAL_PHY(27)
  48. EXTERNAL_PHY(28)
  49. EXTERNAL_PHY(29)
  50. EXTERNAL_PHY(30)
  51. EXTERNAL_PHY(31)
  52. /* External phy RTL8218B #5 */
  53. EXTERNAL_PHY(32)
  54. EXTERNAL_PHY(33)
  55. EXTERNAL_PHY(34)
  56. EXTERNAL_PHY(35)
  57. EXTERNAL_PHY(36)
  58. EXTERNAL_PHY(37)
  59. EXTERNAL_PHY(38)
  60. EXTERNAL_PHY(39)
  61. /* External phy RTL8218B #6 */
  62. EXTERNAL_PHY(40)
  63. EXTERNAL_PHY(41)
  64. EXTERNAL_PHY(42)
  65. EXTERNAL_PHY(43)
  66. EXTERNAL_PHY(44)
  67. EXTERNAL_PHY(45)
  68. EXTERNAL_PHY(46)
  69. EXTERNAL_PHY(47)
  70. /* External phy RTL8214FC */
  71. EXTERNAL_SFP_PHY_FULL(48, 0)
  72. EXTERNAL_SFP_PHY_FULL(49, 1)
  73. EXTERNAL_SFP_PHY_FULL(50, 2)
  74. EXTERNAL_SFP_PHY_FULL(51, 3)
  75. };
  76. };
  77. &switch0 {
  78. ports {
  79. #address-cells = <1>;
  80. #size-cells = <0>;
  81. SWITCH_PORT(0, 1, qsgmii)
  82. SWITCH_PORT(1, 2, qsgmii)
  83. SWITCH_PORT(2, 3, qsgmii)
  84. SWITCH_PORT(3, 4, qsgmii)
  85. SWITCH_PORT(4, 5, qsgmii)
  86. SWITCH_PORT(5, 6, qsgmii)
  87. SWITCH_PORT(6, 7, qsgmii)
  88. SWITCH_PORT(7, 8, qsgmii)
  89. SWITCH_PORT(8, 9, qsgmii)
  90. SWITCH_PORT(9, 10, qsgmii)
  91. SWITCH_PORT(10, 11, qsgmii)
  92. SWITCH_PORT(11, 12, qsgmii)
  93. SWITCH_PORT(12, 13, qsgmii)
  94. SWITCH_PORT(13, 14, qsgmii)
  95. SWITCH_PORT(14, 15, qsgmii)
  96. SWITCH_PORT(15, 16, qsgmii)
  97. SWITCH_PORT(16, 17, qsgmii)
  98. SWITCH_PORT(17, 18, qsgmii)
  99. SWITCH_PORT(18, 19, qsgmii)
  100. SWITCH_PORT(19, 20, qsgmii)
  101. SWITCH_PORT(20, 21, qsgmii)
  102. SWITCH_PORT(21, 22, qsgmii)
  103. SWITCH_PORT(22, 23, qsgmii)
  104. SWITCH_PORT(23, 24, qsgmii)
  105. SWITCH_PORT(24, 25, qsgmii)
  106. SWITCH_PORT(25, 26, qsgmii)
  107. SWITCH_PORT(26, 27, qsgmii)
  108. SWITCH_PORT(27, 28, qsgmii)
  109. SWITCH_PORT(28, 29, qsgmii)
  110. SWITCH_PORT(29, 30, qsgmii)
  111. SWITCH_PORT(30, 31, qsgmii)
  112. SWITCH_PORT(31, 32, qsgmii)
  113. SWITCH_PORT(32, 33, qsgmii)
  114. SWITCH_PORT(33, 34, qsgmii)
  115. SWITCH_PORT(34, 35, qsgmii)
  116. SWITCH_PORT(35, 36, qsgmii)
  117. SWITCH_PORT(36, 37, qsgmii)
  118. SWITCH_PORT(37, 38, qsgmii)
  119. SWITCH_PORT(38, 39, qsgmii)
  120. SWITCH_PORT(39, 40, qsgmii)
  121. SWITCH_PORT(40, 41, qsgmii)
  122. SWITCH_PORT(41, 42, qsgmii)
  123. SWITCH_PORT(42, 43, qsgmii)
  124. SWITCH_PORT(43, 44, qsgmii)
  125. SWITCH_PORT(44, 45, qsgmii)
  126. SWITCH_PORT(45, 46, qsgmii)
  127. SWITCH_PORT(46, 47, qsgmii)
  128. SWITCH_PORT(47, 48, qsgmii)
  129. SWITCH_PORT(48, 49, qsgmii)
  130. SWITCH_PORT(49, 50, qsgmii)
  131. SWITCH_PORT(50, 51, qsgmii)
  132. SWITCH_PORT(51, 52, qsgmii)
  133. /* CPU-Port */
  134. port@52 {
  135. ethernet = <&ethernet0>;
  136. reg = <52>;
  137. phy-mode = "qsgmii";
  138. fixed-link {
  139. speed = <1000>;
  140. full-duplex;
  141. };
  142. };
  143. };
  144. };