rtl930x.dtsi 3.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. /dts-v1/;
  3. / {
  4. #address-cells = <1>;
  5. #size-cells = <1>;
  6. compatible = "realtek,rtl838x-soc";
  7. cpus {
  8. #address-cells = <1>;
  9. #size-cells = <0>;
  10. frequency = <800000000>;
  11. cpu@0 {
  12. compatible = "mips,mips34Kc";
  13. reg = <0>;
  14. };
  15. };
  16. memory@0 {
  17. device_type = "memory";
  18. reg = <0x0 0x8000000>;
  19. };
  20. chosen {
  21. bootargs = "console=ttyS0,115200";
  22. };
  23. cpuintc: cpuintc {
  24. compatible = "mti,cpu-interrupt-controller";
  25. #address-cells = <0>;
  26. #interrupt-cells = <1>;
  27. interrupt-controller;
  28. };
  29. lx_clk: lx_clk {
  30. compatible = "fixed-clock";
  31. #clock-cells = <0>;
  32. clock-frequency = <175000000>;
  33. };
  34. soc: soc {
  35. compatible = "simple-bus";
  36. #address-cells = <1>;
  37. #size-cells = <1>;
  38. ranges = <0x0 0x18000000 0x10000>;
  39. intc: interrupt-controller@3000 {
  40. compatible = "realtek,rtl9300-intc", "realtek,rtl-intc";
  41. reg = <0x3000 0x18>, <0x3018 0x18>;
  42. interrupt-controller;
  43. #interrupt-cells = <2>;
  44. interrupt-parent = <&cpuintc>;
  45. interrupts = <2>, <3>, <4>, <5>, <6>, <7>;
  46. };
  47. rtl9300clock: rtl9300clock@3200 {
  48. compatible = "realtek,rtl9300clock";
  49. reg = <0x3200 0x10>, <0x3210 0x10>;
  50. interrupt-parent = <&intc>;
  51. interrupts = <7 5>, <8 5>;
  52. };
  53. spi0: spi@1200 {
  54. compatible = "realtek,rtl8380-spi";
  55. reg = <0x1200 0x100>;
  56. #address-cells = <1>;
  57. #size-cells = <0>;
  58. };
  59. uart0: uart@2000 {
  60. compatible = "ns16550a";
  61. reg = <0x2000 0x100>;
  62. clocks = <&lx_clk>;
  63. interrupt-parent = <&intc>;
  64. interrupts = <30 1>;
  65. reg-io-width = <1>;
  66. reg-shift = <2>;
  67. fifo-size = <1>;
  68. no-loopback-test;
  69. };
  70. uart1: uart@2100 {
  71. compatible = "ns16550a";
  72. reg = <0x2100 0x100>;
  73. clocks = <&lx_clk>;
  74. interrupt-parent = <&intc>;
  75. interrupts = <31 0>;
  76. reg-io-width = <1>;
  77. reg-shift = <2>;
  78. fifo-size = <1>;
  79. no-loopback-test;
  80. status = "disabled";
  81. };
  82. watchdog0: watchdog@3260 {
  83. compatible = "realtek,rtl9300-wdt";
  84. reg = <0x3260 0xc>;
  85. realtek,reset-mode = "soc";
  86. clocks = <&lx_clk>;
  87. timeout-sec = <30>;
  88. interrupt-parent = <&intc>;
  89. interrupt-names = "phase1", "phase2";
  90. interrupts = <5 4>, <6 4>;
  91. };
  92. gpio0: gpio-controller@3300 {
  93. compatible = "realtek,rtl9300-gpio", "realtek,otto-gpio";
  94. reg = <0x3300 0x1c>, <0x3338 0x8>;
  95. gpio-controller;
  96. #gpio-cells = <2>;
  97. ngpios = <24>;
  98. interrupt-controller;
  99. #interrupt-cells = <2>;
  100. interrupt-parent = <&intc>;
  101. interrupts = <13 1>;
  102. };
  103. };
  104. pinmux_led: pinmux@1b00cc00 {
  105. compatible = "pinctrl-single";
  106. reg = <0x1b00cc00 0x4>;
  107. pinctrl-single,bit-per-mux;
  108. pinctrl-single,register-width = <32>;
  109. pinctrl-single,function-mask = <0x1>;
  110. #pinctrl-cells = <2>;
  111. /* enable GPIO 0 */
  112. pinmux_disable_sys_led: disable_sys_led {
  113. pinctrl-single,bits = <0x0 0x0 0x1000>;
  114. };
  115. };
  116. ethernet0: ethernet@1b00a300 {
  117. compatible = "realtek,rtl838x-eth";
  118. reg = <0x1b00a300 0x100>;
  119. interrupt-parent = <&intc>;
  120. interrupts = <24 3>;
  121. phy-mode = "internal";
  122. fixed-link {
  123. speed = <1000>;
  124. full-duplex;
  125. };
  126. };
  127. switch0: switch@1b000000 {
  128. compatible = "realtek,rtl83xx-switch";
  129. status = "okay";
  130. interrupt-parent = <&intc>;
  131. interrupts = <23 2>;
  132. };
  133. };