093-7-v5.8-ipq806x-PCI-qcom-Add-ipq8064-rev2-variant.patch 1.6 KB

123456789101112131415161718192021222324252627282930313233343536
  1. From 8df093fe2ae1717389df0dcdc620c02cc35abb21 Mon Sep 17 00:00:00 2001
  2. From: Ansuel Smith <[email protected]>
  3. Date: Mon, 15 Jun 2020 23:06:05 +0200
  4. Subject: PCI: qcom: Add ipq8064 rev2 variant
  5. Ipq8064-v2 have tx term offset set to 0. Introduce this variant to permit
  6. different offset based on the revision.
  7. Link: https://lore.kernel.org/r/[email protected]
  8. Signed-off-by: Ansuel Smith <[email protected]>
  9. Signed-off-by: Lorenzo Pieralisi <[email protected]>
  10. Acked-by: Stanimir Varbanov <[email protected]>
  11. ---
  12. drivers/pci/controller/dwc/pcie-qcom.c | 4 +++-
  13. 1 file changed, 3 insertions(+), 1 deletion(-)
  14. --- a/drivers/pci/controller/dwc/pcie-qcom.c
  15. +++ b/drivers/pci/controller/dwc/pcie-qcom.c
  16. @@ -368,7 +368,8 @@ static int qcom_pcie_init_2_1_0(struct q
  17. val &= ~BIT(0);
  18. writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
  19. - if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
  20. + if (of_device_is_compatible(node, "qcom,pcie-ipq8064") ||
  21. + of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) {
  22. writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
  23. PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
  24. PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
  25. @@ -1328,6 +1329,7 @@ err_pm_runtime_put:
  26. static const struct of_device_id qcom_pcie_match[] = {
  27. { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
  28. { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
  29. + { .compatible = "qcom,pcie-ipq8064-v2", .data = &ops_2_1_0 },
  30. { .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },
  31. { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
  32. { .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },