300-clk-qcom-ipq4019-add-ess-reset.patch 1.7 KB

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  1. From 480c1f7648fc586db12d6003c717c23667a4fcf0 Mon Sep 17 00:00:00 2001
  2. From: Ram Chandra Jangir <[email protected]>
  3. Date: Tue, 28 Mar 2017 22:35:33 +0530
  4. Subject: [PATCH] clk: qcom: ipq4019: add ess reset
  5. Added the ESS reset in IPQ4019 GCC.
  6. Signed-off-by: Ram Chandra Jangir <[email protected]>
  7. ---
  8. drivers/clk/qcom/gcc-ipq4019.c | 11 +++++++++++
  9. include/dt-bindings/clock/qcom,gcc-ipq4019.h | 11 +++++++++++
  10. 2 files changed, 22 insertions(+)
  11. --- a/drivers/clk/qcom/gcc-ipq4019.c
  12. +++ b/drivers/clk/qcom/gcc-ipq4019.c
  13. @@ -1736,6 +1736,17 @@ static const struct qcom_reset_map gcc_i
  14. [GCC_TCSR_BCR] = {0x22000, 0},
  15. [GCC_MPM_BCR] = {0x24000, 0},
  16. [GCC_SPDM_BCR] = {0x25000, 0},
  17. + [ESS_MAC1_ARES] = {0x1200C, 0},
  18. + [ESS_MAC2_ARES] = {0x1200C, 1},
  19. + [ESS_MAC3_ARES] = {0x1200C, 2},
  20. + [ESS_MAC4_ARES] = {0x1200C, 3},
  21. + [ESS_MAC5_ARES] = {0x1200C, 4},
  22. + [ESS_PSGMII_ARES] = {0x1200C, 5},
  23. + [ESS_MAC1_CLK_DIS] = {0x1200C, 8},
  24. + [ESS_MAC2_CLK_DIS] = {0x1200C, 9},
  25. + [ESS_MAC3_CLK_DIS] = {0x1200C, 10},
  26. + [ESS_MAC4_CLK_DIS] = {0x1200C, 11},
  27. + [ESS_MAC5_CLK_DIS] = {0x1200C, 12},
  28. };
  29. static const struct regmap_config gcc_ipq4019_regmap_config = {
  30. --- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h
  31. +++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h
  32. @@ -165,5 +165,16 @@
  33. #define GCC_QDSS_BCR 69
  34. #define GCC_MPM_BCR 70
  35. #define GCC_SPDM_BCR 71
  36. +#define ESS_MAC1_ARES 72
  37. +#define ESS_MAC2_ARES 73
  38. +#define ESS_MAC3_ARES 74
  39. +#define ESS_MAC4_ARES 75
  40. +#define ESS_MAC5_ARES 76
  41. +#define ESS_PSGMII_ARES 77
  42. +#define ESS_MAC1_CLK_DIS 78
  43. +#define ESS_MAC2_CLK_DIS 79
  44. +#define ESS_MAC3_CLK_DIS 80
  45. +#define ESS_MAC4_CLK_DIS 81
  46. +#define ESS_MAC5_CLK_DIS 82
  47. #endif