0027-MIPS-ath79-drop-legacy-IRQ-code.patch 6.1 KB

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  1. From 3765b1f79593a0a9098ed15e48074c95403a53ee Mon Sep 17 00:00:00 2001
  2. From: John Crispin <[email protected]>
  3. Date: Sat, 23 Jun 2018 15:05:08 +0200
  4. Subject: [PATCH 27/33] MIPS: ath79: drop legacy IRQ code
  5. With the target now being fully OF based, we can drop the legacy IRQ code.
  6. All IRQs are now handled via the new irqchip drivers.
  7. Signed-off-by: John Crispin <[email protected]>
  8. ---
  9. arch/mips/ath79/Makefile | 2 +-
  10. arch/mips/ath79/irq.c | 169 -------------------------------
  11. arch/mips/ath79/setup.c | 6 ++
  12. arch/mips/include/asm/mach-ath79/ath79.h | 4 -
  13. 4 files changed, 7 insertions(+), 174 deletions(-)
  14. delete mode 100644 arch/mips/ath79/irq.c
  15. --- a/arch/mips/ath79/Makefile
  16. +++ b/arch/mips/ath79/Makefile
  17. @@ -8,7 +8,7 @@
  18. # under the terms of the GNU General Public License version 2 as published
  19. # by the Free Software Foundation.
  20. -obj-y := prom.o setup.o irq.o common.o clock.o
  21. +obj-y := prom.o setup.o common.o clock.o
  22. obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
  23. obj-$(CONFIG_PCI) += pci.o
  24. --- a/arch/mips/ath79/irq.c
  25. +++ /dev/null
  26. @@ -1,169 +0,0 @@
  27. -/*
  28. - * Atheros AR71xx/AR724x/AR913x specific interrupt handling
  29. - *
  30. - * Copyright (C) 2010-2011 Jaiganesh Narayanan <[email protected]>
  31. - * Copyright (C) 2008-2011 Gabor Juhos <[email protected]>
  32. - * Copyright (C) 2008 Imre Kaloz <[email protected]>
  33. - *
  34. - * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
  35. - *
  36. - * This program is free software; you can redistribute it and/or modify it
  37. - * under the terms of the GNU General Public License version 2 as published
  38. - * by the Free Software Foundation.
  39. - */
  40. -
  41. -#include <linux/kernel.h>
  42. -#include <linux/init.h>
  43. -#include <linux/interrupt.h>
  44. -#include <linux/irqchip.h>
  45. -#include <linux/of_irq.h>
  46. -
  47. -#include <asm/irq_cpu.h>
  48. -#include <asm/mipsregs.h>
  49. -
  50. -#include <asm/mach-ath79/ath79.h>
  51. -#include <asm/mach-ath79/ar71xx_regs.h>
  52. -#include "common.h"
  53. -#include "machtypes.h"
  54. -
  55. -
  56. -static void ar934x_ip2_irq_dispatch(struct irq_desc *desc)
  57. -{
  58. - u32 status;
  59. -
  60. - status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
  61. -
  62. - if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
  63. - ath79_ddr_wb_flush(3);
  64. - generic_handle_irq(ATH79_IP2_IRQ(0));
  65. - } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
  66. - ath79_ddr_wb_flush(4);
  67. - generic_handle_irq(ATH79_IP2_IRQ(1));
  68. - } else {
  69. - spurious_interrupt();
  70. - }
  71. -}
  72. -
  73. -static void ar934x_ip2_irq_init(void)
  74. -{
  75. - int i;
  76. -
  77. - for (i = ATH79_IP2_IRQ_BASE;
  78. - i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
  79. - irq_set_chip_and_handler(i, &dummy_irq_chip,
  80. - handle_level_irq);
  81. -
  82. - irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
  83. -}
  84. -
  85. -static void qca955x_ip2_irq_dispatch(struct irq_desc *desc)
  86. -{
  87. - u32 status;
  88. -
  89. - status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
  90. - status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL;
  91. -
  92. - if (status == 0) {
  93. - spurious_interrupt();
  94. - return;
  95. - }
  96. -
  97. - if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
  98. - /* TODO: flush DDR? */
  99. - generic_handle_irq(ATH79_IP2_IRQ(0));
  100. - }
  101. -
  102. - if (status & QCA955X_EXT_INT_WMAC_ALL) {
  103. - /* TODO: flush DDR? */
  104. - generic_handle_irq(ATH79_IP2_IRQ(1));
  105. - }
  106. -}
  107. -
  108. -static void qca955x_ip3_irq_dispatch(struct irq_desc *desc)
  109. -{
  110. - u32 status;
  111. -
  112. - status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
  113. - status &= QCA955X_EXT_INT_PCIE_RC2_ALL |
  114. - QCA955X_EXT_INT_USB1 |
  115. - QCA955X_EXT_INT_USB2;
  116. -
  117. - if (status == 0) {
  118. - spurious_interrupt();
  119. - return;
  120. - }
  121. -
  122. - if (status & QCA955X_EXT_INT_USB1) {
  123. - /* TODO: flush DDR? */
  124. - generic_handle_irq(ATH79_IP3_IRQ(0));
  125. - }
  126. -
  127. - if (status & QCA955X_EXT_INT_USB2) {
  128. - /* TODO: flush DDR? */
  129. - generic_handle_irq(ATH79_IP3_IRQ(1));
  130. - }
  131. -
  132. - if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) {
  133. - /* TODO: flush DDR? */
  134. - generic_handle_irq(ATH79_IP3_IRQ(2));
  135. - }
  136. -}
  137. -
  138. -static void qca955x_irq_init(void)
  139. -{
  140. - int i;
  141. -
  142. - for (i = ATH79_IP2_IRQ_BASE;
  143. - i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
  144. - irq_set_chip_and_handler(i, &dummy_irq_chip,
  145. - handle_level_irq);
  146. -
  147. - irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
  148. -
  149. - for (i = ATH79_IP3_IRQ_BASE;
  150. - i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
  151. - irq_set_chip_and_handler(i, &dummy_irq_chip,
  152. - handle_level_irq);
  153. -
  154. - irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
  155. -}
  156. -
  157. -void __init arch_init_irq(void)
  158. -{
  159. - unsigned irq_wb_chan2 = -1;
  160. - unsigned irq_wb_chan3 = -1;
  161. - bool misc_is_ar71xx;
  162. -
  163. - if (mips_machtype == ATH79_MACH_GENERIC_OF) {
  164. - irqchip_init();
  165. - return;
  166. - }
  167. -
  168. - if (soc_is_ar71xx() || soc_is_ar724x() ||
  169. - soc_is_ar913x() || soc_is_ar933x()) {
  170. - irq_wb_chan2 = 3;
  171. - irq_wb_chan3 = 2;
  172. - } else if (soc_is_ar934x()) {
  173. - irq_wb_chan3 = 2;
  174. - }
  175. -
  176. - ath79_cpu_irq_init(irq_wb_chan2, irq_wb_chan3);
  177. -
  178. - if (soc_is_ar71xx() || soc_is_ar913x())
  179. - misc_is_ar71xx = true;
  180. - else if (soc_is_ar724x() ||
  181. - soc_is_ar933x() ||
  182. - soc_is_ar934x() ||
  183. - soc_is_qca955x())
  184. - misc_is_ar71xx = false;
  185. - else
  186. - BUG();
  187. - ath79_misc_irq_init(
  188. - ath79_reset_base + AR71XX_RESET_REG_MISC_INT_STATUS,
  189. - ATH79_CPU_IRQ(6), ATH79_MISC_IRQ_BASE, misc_is_ar71xx);
  190. -
  191. - if (soc_is_ar934x())
  192. - ar934x_ip2_irq_init();
  193. - else if (soc_is_qca955x())
  194. - qca955x_irq_init();
  195. -}
  196. --- a/arch/mips/ath79/setup.c
  197. +++ b/arch/mips/ath79/setup.c
  198. @@ -19,6 +19,7 @@
  199. #include <linux/clk.h>
  200. #include <linux/clk-provider.h>
  201. #include <linux/of_fdt.h>
  202. +#include <linux/irqchip.h>
  203. #include <asm/bootinfo.h>
  204. #include <asm/idle.h>
  205. @@ -311,6 +312,11 @@ void __init plat_time_init(void)
  206. mips_hpt_frequency = cpu_clk_rate / 2;
  207. }
  208. +void __init arch_init_irq(void)
  209. +{
  210. + irqchip_init();
  211. +}
  212. +
  213. static int __init ath79_setup(void)
  214. {
  215. if (mips_machtype == ATH79_MACH_GENERIC_OF)
  216. --- a/arch/mips/include/asm/mach-ath79/ath79.h
  217. +++ b/arch/mips/include/asm/mach-ath79/ath79.h
  218. @@ -178,8 +178,4 @@ static inline u32 ath79_reset_rr(unsigne
  219. void ath79_device_reset_set(u32 mask);
  220. void ath79_device_reset_clear(u32 mask);
  221. -void ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3);
  222. -void ath79_misc_irq_init(void __iomem *regs, int irq,
  223. - int irq_base, bool is_ar71xx);
  224. -
  225. #endif /* __ASM_MACH_ATH79_H */