qcom-ipq4019-le1.dts 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "qcom-ipq4019.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. #include <dt-bindings/soc/qcom,tcsr.h>
  6. / {
  7. model = "YYeTs LE1";
  8. compatible = "yyets,le1";
  9. aliases {
  10. led-boot = &led_usb;
  11. led-failsafe = &led_usb;
  12. led-upgrade = &led_usb;
  13. ethernet0 = &swport5;
  14. ethernet1 = &gmac;
  15. label-mac-device = &gmac;
  16. };
  17. keys {
  18. compatible = "gpio-keys";
  19. reset {
  20. label = "reset";
  21. gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
  22. linux,code = <KEY_RESTART>;
  23. };
  24. };
  25. leds {
  26. compatible = "gpio-leds";
  27. led_usb: usb {
  28. label = "green:usb";
  29. gpios = <&tlmm 36 GPIO_ACTIVE_LOW>;
  30. linux,default-trigger = "usbport";
  31. trigger-sources = <&usb3_port1>, <&usb3_port2>, <&usb2_port1>;
  32. };
  33. wlan2g {
  34. label = "green:wlan2g";
  35. gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
  36. linux,default-trigger = "phy0tpt";
  37. };
  38. wlan5g {
  39. label = "green:wlan5g";
  40. gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
  41. linux,default-trigger = "phy1tpt";
  42. };
  43. };
  44. soc {
  45. tcsr@1949000 {
  46. compatible = "qcom,tcsr";
  47. reg = <0x1949000 0x100>;
  48. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  49. };
  50. tcsr@194b000 {
  51. compatible = "qcom,tcsr";
  52. reg = <0x194b000 0x100>;
  53. qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  54. };
  55. ess_tcsr@1953000 {
  56. compatible = "qcom,tcsr";
  57. reg = <0x1953000 0x1000>;
  58. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  59. };
  60. tcsr@1957000 {
  61. compatible = "qcom,tcsr";
  62. reg = <0x1957000 0x100>;
  63. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  64. };
  65. };
  66. };
  67. &blsp_dma {
  68. status = "okay";
  69. };
  70. &blsp1_spi1 {
  71. cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
  72. pinctrl-0 = <&spi_0_pins>;
  73. pinctrl-names = "default";
  74. status = "okay";
  75. flash@0 {
  76. compatible = "jedec,spi-nor";
  77. #address-cells = <1>;
  78. #size-cells = <1>;
  79. reg = <0>;
  80. spi-max-frequency = <24000000>;
  81. partitions {
  82. compatible = "fixed-partitions";
  83. #address-cells = <1>;
  84. #size-cells = <1>;
  85. partition@0 {
  86. label = "SBL1";
  87. reg = <0x0 0x40000>;
  88. read-only;
  89. };
  90. partition@40000 {
  91. label = "MIBIB";
  92. reg = <0x40000 0x20000>;
  93. read-only;
  94. };
  95. partition@60000 {
  96. label = "QSEE";
  97. reg = <0x60000 0x60000>;
  98. read-only;
  99. };
  100. partition@c0000 {
  101. label = "CDT";
  102. reg = <0xc0000 0x10000>;
  103. read-only;
  104. };
  105. partition@d0000 {
  106. label = "DDRPARAMS";
  107. reg = <0xd0000 0x10000>;
  108. read-only;
  109. };
  110. partition@e0000 {
  111. label = "APPSBLENV";
  112. reg = <0xe0000 0x10000>;
  113. read-only;
  114. };
  115. partition@f0000 {
  116. label = "APPSBL";
  117. reg = <0xf0000 0x80000>;
  118. read-only;
  119. };
  120. partition@170000 {
  121. label = "ART";
  122. reg = <0x170000 0x10000>;
  123. read-only;
  124. compatible = "nvmem-cells";
  125. #address-cells = <1>;
  126. #size-cells = <1>;
  127. precal_art_1000: precal@1000 {
  128. reg = <0x1000 0x2f20>;
  129. };
  130. precal_art_5000: precal@5000 {
  131. reg = <0x5000 0x2f20>;
  132. };
  133. };
  134. partition@180000 {
  135. compatible = "denx,fit";
  136. label = "firmware";
  137. reg = <0x180000 0x1e80000>;
  138. };
  139. };
  140. };
  141. };
  142. &blsp1_uart1 {
  143. pinctrl-0 = <&serial_pins>;
  144. pinctrl-names = "default";
  145. status = "okay";
  146. };
  147. &cryptobam {
  148. status = "okay";
  149. };
  150. &crypto {
  151. status = "okay";
  152. };
  153. &gmac {
  154. status = "okay";
  155. };
  156. &mdio {
  157. pinctrl-0 = <&mdio_pins>;
  158. pinctrl-names = "default";
  159. status = "okay";
  160. };
  161. &prng {
  162. status = "okay";
  163. };
  164. &switch {
  165. status = "okay";
  166. };
  167. &swport1 {
  168. status = "okay";
  169. };
  170. &swport2 {
  171. status = "okay";
  172. };
  173. &swport3 {
  174. status = "okay";
  175. };
  176. &swport4 {
  177. status = "okay";
  178. };
  179. &swport5 {
  180. status = "okay";
  181. };
  182. &tlmm {
  183. mdio_pins: mdio_pinmux {
  184. mux_1 {
  185. pins = "gpio6";
  186. function = "mdio";
  187. bias-pull-up;
  188. };
  189. mux_2 {
  190. pins = "gpio7";
  191. function = "mdc";
  192. bias-pull-up;
  193. };
  194. };
  195. serial_pins: serial_pinmux {
  196. mux {
  197. pins = "gpio16", "gpio17";
  198. function = "blsp_uart0";
  199. bias-disable;
  200. };
  201. };
  202. spi_0_pins: spi_0_pinmux {
  203. pinmux {
  204. function = "blsp_spi0";
  205. pins = "gpio13", "gpio14", "gpio15";
  206. drive-strength = <12>;
  207. bias-disable;
  208. };
  209. pinmux_cs {
  210. function = "gpio";
  211. pins = "gpio12";
  212. drive-strength = <2>;
  213. bias-disable;
  214. output-high;
  215. };
  216. };
  217. };
  218. &usb2 {
  219. status = "okay";
  220. dwc3@6000000 {
  221. #address-cells = <1>;
  222. #size-cells = <0>;
  223. usb2_port1: port@1 {
  224. reg = <1>;
  225. #trigger-source-cells = <0>;
  226. };
  227. };
  228. };
  229. &usb2_hs_phy {
  230. status = "okay";
  231. };
  232. &usb3 {
  233. status = "okay";
  234. dwc3@8a00000 {
  235. #address-cells = <1>;
  236. #size-cells = <0>;
  237. usb3_port1: port@1 {
  238. reg = <1>;
  239. #trigger-source-cells = <0>;
  240. };
  241. usb3_port2: port@2 {
  242. reg = <2>;
  243. #trigger-source-cells = <0>;
  244. };
  245. };
  246. };
  247. &usb3_hs_phy {
  248. status = "okay";
  249. };
  250. &usb3_ss_phy {
  251. status = "okay";
  252. };
  253. &watchdog {
  254. status = "okay";
  255. };
  256. &wifi0 {
  257. status = "okay";
  258. nvmem-cells = <&precal_art_1000>;
  259. nvmem-cell-names = "pre-calibration";
  260. qcom,ath10k-calibration-variant = "YYeTs-LE1";
  261. };
  262. &wifi1 {
  263. status = "okay";
  264. nvmem-cells = <&precal_art_5000>;
  265. nvmem-cell-names = "pre-calibration";
  266. qcom,ath10k-calibration-variant = "YYeTs-LE1";
  267. };