mt7620a_head-weblink_hdrm200.dts 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. /dts-v1/;
  3. #include "mt7620a.dtsi"
  4. #include <dt-bindings/gpio/gpio.h>
  5. #include <dt-bindings/input/input.h>
  6. / {
  7. compatible = "head-weblink,hdrm200", "ralink,mt7620a-soc";
  8. model = "Head Weblink HDRM200";
  9. aliases {
  10. led-boot = &led_system;
  11. led-failsafe = &led_system;
  12. led-running = &led_system;
  13. led-upgrade = &led_system;
  14. };
  15. chosen {
  16. bootargs = "console=ttyS1,57600";
  17. };
  18. leds {
  19. compatible = "gpio-leds";
  20. rssi {
  21. label = "hdrm200:red:rssi";
  22. gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
  23. };
  24. led_system: system {
  25. label = "hdrm200:green:system";
  26. gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
  27. };
  28. air {
  29. label = "hdrm200:green:wifi";
  30. gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
  31. };
  32. };
  33. keys {
  34. compatible = "gpio-keys";
  35. wps {
  36. label = "wps";
  37. gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
  38. linux,code = <KEY_WPS_BUTTON>;
  39. };
  40. reset {
  41. label = "reset";
  42. gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
  43. linux,code = <KEY_RESTART>;
  44. };
  45. };
  46. };
  47. &spi0 {
  48. status = "okay";
  49. flash@0 {
  50. compatible = "jedec,spi-nor";
  51. reg = <0>;
  52. spi-max-frequency = <10000000>;
  53. partitions {
  54. compatible = "fixed-partitions";
  55. #address-cells = <1>;
  56. #size-cells = <1>;
  57. partition@0 {
  58. label = "u-boot";
  59. reg = <0x0 0x30000>;
  60. read-only;
  61. };
  62. partition@30000 {
  63. label = "u-boot-env";
  64. reg = <0x30000 0x10000>;
  65. read-only;
  66. };
  67. factory: partition@40000 {
  68. label = "factory";
  69. reg = <0x40000 0x10000>;
  70. read-only;
  71. };
  72. firmware: partition@50000 {
  73. compatible = "denx,uimage";
  74. label = "firmware";
  75. reg = <0x50000 0xfb0000>;
  76. };
  77. };
  78. };
  79. };
  80. &gpio0 {
  81. status = "okay";
  82. };
  83. &gpio1 {
  84. status = "okay";
  85. };
  86. &gpio3 {
  87. status = "okay";
  88. };
  89. &sdhci {
  90. status = "okay";
  91. };
  92. &ehci {
  93. status = "okay";
  94. };
  95. &ohci {
  96. status = "okay";
  97. };
  98. &ethernet {
  99. status = "okay";
  100. mtd-mac-address = <&factory 0x4>;
  101. pinctrl-names = "default";
  102. pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
  103. port@4 {
  104. status = "okay";
  105. phy-handle = <&phy4>;
  106. phy-mode = "rgmii";
  107. };
  108. port@5 {
  109. status = "okay";
  110. phy-handle = <&phy5>;
  111. phy-mode = "rgmii";
  112. };
  113. mdio-bus {
  114. status = "okay";
  115. phy4: ethernet-phy@4 {
  116. reg = <4>;
  117. phy-mode = "rgmii";
  118. };
  119. phy5: ethernet-phy@5 {
  120. reg = <5>;
  121. phy-mode = "rgmii";
  122. };
  123. };
  124. };
  125. &wmac {
  126. ralink,mtd-eeprom = <&factory 0>;
  127. };
  128. &state_default {
  129. default {
  130. ralink,group = "i2c", "uartf", "pa", "spi refclk",
  131. "wled";
  132. ralink,function = "gpio";
  133. };
  134. };
  135. &pcie {
  136. status = "okay";
  137. };
  138. &pcie0 {
  139. wifi@0,0 {
  140. compatible = "mediatek,mt76";
  141. reg = <0x0000 0 0 0 0>;
  142. mediatek,mtd-eeprom = <&factory 0x8000>;
  143. ieee80211-freq-limit = <5000000 6000000>;
  144. };
  145. };
  146. &uart {
  147. status = "okay";
  148. };