101-mt7621-timer.patch 1.9 KB

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  1. --- a/arch/mips/ralink/mt7621.c
  2. +++ b/arch/mips/ralink/mt7621.c
  3. @@ -9,6 +9,7 @@
  4. #include <linux/kernel.h>
  5. #include <linux/init.h>
  6. +#include <linux/jiffies.h>
  7. #include <asm/mipsregs.h>
  8. #include <asm/smp-ops.h>
  9. @@ -16,6 +17,7 @@
  10. #include <asm/mach-ralink/ralink_regs.h>
  11. #include <asm/mach-ralink/mt7621.h>
  12. #include <asm/mips-boards/launch.h>
  13. +#include <asm/delay.h>
  14. #include <pinmux.h>
  15. @@ -177,6 +179,58 @@ bool plat_cpu_core_present(int core)
  16. return true;
  17. }
  18. +#define LPS_PREC 8
  19. +/*
  20. +* Re-calibration lpj(loop-per-jiffy).
  21. +* (derived from kernel/calibrate.c)
  22. +*/
  23. +static int udelay_recal(void)
  24. +{
  25. + unsigned int i, lpj = 0;
  26. + unsigned long ticks, loopbit;
  27. + int lps_precision = LPS_PREC;
  28. +
  29. + lpj = (1<<12);
  30. +
  31. + while ((lpj <<= 1) != 0) {
  32. + /* wait for "start of" clock tick */
  33. + ticks = jiffies;
  34. + while (ticks == jiffies)
  35. + /* nothing */;
  36. +
  37. + /* Go .. */
  38. + ticks = jiffies;
  39. + __delay(lpj);
  40. + ticks = jiffies - ticks;
  41. + if (ticks)
  42. + break;
  43. + }
  44. +
  45. + /*
  46. + * Do a binary approximation to get lpj set to
  47. + * equal one clock (up to lps_precision bits)
  48. + */
  49. + lpj >>= 1;
  50. + loopbit = lpj;
  51. + while (lps_precision-- && (loopbit >>= 1)) {
  52. + lpj |= loopbit;
  53. + ticks = jiffies;
  54. + while (ticks == jiffies)
  55. + /* nothing */;
  56. + ticks = jiffies;
  57. + __delay(lpj);
  58. + if (jiffies != ticks) /* longer than 1 tick */
  59. + lpj &= ~loopbit;
  60. + }
  61. + printk(KERN_INFO "%d CPUs re-calibrate udelay(lpj = %d)\n", NR_CPUS, lpj);
  62. +
  63. + for(i=0; i< NR_CPUS; i++)
  64. + cpu_data[i].udelay_val = lpj;
  65. +
  66. + return 0;
  67. +}
  68. +device_initcall(udelay_recal);
  69. +
  70. void prom_soc_init(struct ralink_soc_info *soc_info)
  71. {
  72. void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
  73. --- a/arch/mips/ralink/Kconfig
  74. +++ b/arch/mips/ralink/Kconfig
  75. @@ -59,6 +59,7 @@ choice
  76. select CLKSRC_MIPS_GIC
  77. select HW_HAS_PCI
  78. select WEAK_REORDERING_BEYOND_LLSC
  79. + select GENERIC_CLOCKEVENTS_BROADCAST
  80. endchoice
  81. choice