mt7986a-bananapi-bpi-r3.dts 16 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Copyright (C) 2021 MediaTek Inc.
  4. * Author: Sam.Shih <[email protected]>
  5. */
  6. /dts-v1/;
  7. #include <dt-bindings/input/input.h>
  8. #include <dt-bindings/gpio/gpio.h>
  9. #include "mt7986a.dtsi"
  10. / {
  11. model = "Bananapi BPI-R3";
  12. compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
  13. aliases {
  14. serial0 = &uart0;
  15. ethernet0 = &gmac0;
  16. ethernet1 = &gmac1;
  17. led-boot = &led_status_green;
  18. led-failsafe = &led_status_green;
  19. led-running = &led_status_green;
  20. led-upgrade = &led_status_blue;
  21. };
  22. chosen {
  23. stdout-path = "serial0:115200n8";
  24. };
  25. memory@40000000 {
  26. device_type = "memory";
  27. reg = <0 0x40000000 0 0x40000000>;
  28. };
  29. reg_1p8v: regulator-1p8v {
  30. compatible = "regulator-fixed";
  31. regulator-name = "fixed-1.8V";
  32. regulator-min-microvolt = <1800000>;
  33. regulator-max-microvolt = <1800000>;
  34. regulator-boot-on;
  35. regulator-always-on;
  36. };
  37. reg_3p3v: regulator-3p3v {
  38. compatible = "regulator-fixed";
  39. regulator-name = "fixed-3.3V";
  40. regulator-min-microvolt = <3300000>;
  41. regulator-max-microvolt = <3300000>;
  42. regulator-boot-on;
  43. regulator-always-on;
  44. };
  45. reg_5v: regulator-5v {
  46. compatible = "regulator-fixed";
  47. regulator-name = "fixed-5V";
  48. regulator-min-microvolt = <5000000>;
  49. regulator-max-microvolt = <5000000>;
  50. regulator-boot-on;
  51. regulator-always-on;
  52. };
  53. keys {
  54. compatible = "gpio-keys";
  55. /*
  56. * RST button is also PCIe-CLKREQ signal, use WPS button as reset
  57. * instead as RST button doesn't make sense and cannot be used.
  58. *
  59. * intended buttons:
  60. factory {
  61. label = "reset";
  62. linux,code = <KEY_RESTART>;
  63. gpios = <&pio 9 GPIO_ACTIVE_LOW>;
  64. };
  65. wps {
  66. label = "wps";
  67. linux,code = <KEY_WPS_BUTTON>;
  68. gpios = <&pio 10 GPIO_ACTIVE_LOW>;
  69. };
  70. * actual setup:
  71. */
  72. wps {
  73. label = "wps";
  74. linux,code = <KEY_RESTART>;
  75. gpios = <&pio 10 GPIO_ACTIVE_LOW>;
  76. };
  77. };
  78. leds {
  79. compatible = "gpio-leds";
  80. led_status_green: green {
  81. label = "green:status";
  82. gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
  83. default-state = "on";
  84. };
  85. led_status_blue: blue {
  86. label = "blue:status";
  87. gpios = <&pio 86 GPIO_ACTIVE_HIGH>;
  88. };
  89. };
  90. /* SFP1 cage (WAN) */
  91. i2c_sfp1: i2c-gpio-0 {
  92. compatible = "i2c-gpio";
  93. sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  94. scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  95. i2c-gpio,delay-us = <2>;
  96. #address-cells = <1>;
  97. #size-cells = <0>;
  98. };
  99. sfp1: sfp1 {
  100. compatible = "sff,sfp";
  101. i2c-bus = <&i2c_sfp1>;
  102. los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
  103. mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
  104. tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
  105. tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
  106. };
  107. /* SFP2 cage (LAN) */
  108. i2c_sfp2: i2c-gpio-1 {
  109. compatible = "i2c-gpio";
  110. sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  111. scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  112. i2c-gpio,delay-us = <2>;
  113. #address-cells = <1>;
  114. #size-cells = <0>;
  115. };
  116. sfp2: sfp2 {
  117. compatible = "sff,sfp";
  118. i2c-bus = <&i2c_sfp2>;
  119. los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
  120. mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
  121. tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
  122. tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
  123. };
  124. };
  125. &eth {
  126. status = "okay";
  127. gmac0: mac@0 {
  128. compatible = "mediatek,eth-mac";
  129. reg = <0>;
  130. phy-mode = "2500base-x";
  131. fixed-link {
  132. speed = <2500>;
  133. full-duplex;
  134. pause;
  135. };
  136. };
  137. gmac1: mac@1 {
  138. compatible = "mediatek,eth-mac";
  139. reg = <1>;
  140. phy-mode = "2500base-x";
  141. sfp = <&sfp1>;
  142. managed = "in-band-status";
  143. };
  144. mdio: mdio-bus {
  145. #address-cells = <1>;
  146. #size-cells = <0>;
  147. };
  148. };
  149. &mdio {
  150. switch: switch@0 {
  151. compatible = "mediatek,mt7531";
  152. reg = <31>;
  153. reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>;
  154. interrupt-controller;
  155. #interrupt-cells = <1>;
  156. interrupt-parent = <&pio>;
  157. interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
  158. };
  159. };
  160. &switch {
  161. ports {
  162. #address-cells = <1>;
  163. #size-cells = <0>;
  164. port@0 {
  165. reg = <0>;
  166. label = "wan";
  167. };
  168. port@1 {
  169. reg = <1>;
  170. label = "lan1";
  171. };
  172. port@2 {
  173. reg = <2>;
  174. label = "lan2";
  175. };
  176. port@3 {
  177. reg = <3>;
  178. label = "lan3";
  179. };
  180. port@4 {
  181. reg = <4>;
  182. label = "lan4";
  183. };
  184. port5: port@5 {
  185. reg = <5>;
  186. label = "sfp2";
  187. phy-mode = "2500base-x";
  188. sfp = <&sfp2>;
  189. managed = "in-band-status";
  190. };
  191. port@6 {
  192. reg = <6>;
  193. ethernet = <&gmac0>;
  194. phy-mode = "2500base-x";
  195. fixed-link {
  196. speed = <2500>;
  197. full-duplex;
  198. pause;
  199. };
  200. };
  201. };
  202. };
  203. &crypto {
  204. status = "okay";
  205. };
  206. &mmc0 {
  207. //sdcard
  208. pinctrl-names = "default", "state_uhs";
  209. pinctrl-0 = <&mmc0_pins_default>;
  210. pinctrl-1 = <&mmc0_pins_uhs>;
  211. bus-width = <4>;
  212. max-frequency = <52000000>;
  213. cap-sd-highspeed;
  214. vmmc-supply = <&reg_3p3v>;
  215. vqmmc-supply = <&reg_1p8v>;
  216. status = "okay";
  217. };
  218. &pcie {
  219. pinctrl-names = "default";
  220. pinctrl-0 = <&pcie_pins>;
  221. status = "okay";
  222. };
  223. &pcie_phy {
  224. status = "okay";
  225. };
  226. &wmac {
  227. status = "okay";
  228. pinctrl-names = "default", "dbdc";
  229. pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
  230. pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
  231. };
  232. &pio {
  233. /* don't mess around with GPIO 419, 450, 451, 498, 510 in sysfs system will freeze. */
  234. mmc0_pins_default: mmc0-pins {
  235. mux {
  236. function = "emmc";
  237. groups = "emmc_51";
  238. };
  239. conf-cmd-dat {
  240. pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
  241. "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
  242. "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
  243. input-enable;
  244. drive-strength = <4>;
  245. mediatek,pull-up-adv = <1>; /* pull-up 10K */
  246. };
  247. conf-clk {
  248. pins = "EMMC_CK";
  249. drive-strength = <6>;
  250. mediatek,pull-down-adv = <2>; /* pull-down 50K */
  251. };
  252. conf-ds {
  253. pins = "EMMC_DSL";
  254. mediatek,pull-down-adv = <2>; /* pull-down 50K */
  255. };
  256. conf-rst {
  257. pins = "EMMC_RSTB";
  258. drive-strength = <4>;
  259. mediatek,pull-up-adv = <1>; /* pull-up 10K */
  260. };
  261. };
  262. mmc0_pins_uhs: mmc0-uhs-pins {
  263. mux {
  264. function = "emmc";
  265. groups = "emmc_51";
  266. };
  267. conf-cmd-dat {
  268. pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
  269. "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
  270. "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
  271. input-enable;
  272. drive-strength = <4>;
  273. mediatek,pull-up-adv = <1>; /* pull-up 10K */
  274. };
  275. conf-clk {
  276. pins = "EMMC_CK";
  277. drive-strength = <6>;
  278. mediatek,pull-down-adv = <2>; /* pull-down 50K */
  279. };
  280. conf-ds {
  281. pins = "EMMC_DSL";
  282. mediatek,pull-down-adv = <2>; /* pull-down 50K */
  283. };
  284. conf-rst {
  285. pins = "EMMC_RSTB";
  286. drive-strength = <4>;
  287. mediatek,pull-up-adv = <1>; /* pull-up 10K */
  288. };
  289. };
  290. pcie_pins: pcie-pins {
  291. mux {
  292. function = "pcie";
  293. groups = "pcie_clk", "pcie_pereset"; //"pcie_wake" is unused
  294. };
  295. };
  296. spi_flash_pins: spi-flash-pins {
  297. mux {
  298. function = "spi";
  299. groups = "spi0", "spi0_wp_hold";
  300. };
  301. };
  302. uart1_pins: uart1-pins {
  303. mux {
  304. function = "uart";
  305. groups = "uart1";
  306. };
  307. };
  308. i2c0_pins: i2c0-pins {
  309. mux {
  310. function = "i2c";
  311. groups = "i2c";
  312. };
  313. };
  314. pwm_pins: pwm-pins {
  315. mux {
  316. function = "pwm";
  317. groups = "pwm0", "pwm1_0";
  318. };
  319. };
  320. wf_led_pins: wf-led-pins {
  321. mux {
  322. function = "led";
  323. groups = "wifi_led";
  324. };
  325. };
  326. wf_2g_5g_pins: wf-2g-5g-pins {
  327. mux {
  328. function = "wifi";
  329. groups = "wf_2g", "wf_5g";
  330. };
  331. conf {
  332. pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
  333. "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
  334. "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
  335. "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
  336. "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
  337. "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
  338. "WF1_TOP_CLK", "WF1_TOP_DATA";
  339. drive-strength = <4>;
  340. };
  341. };
  342. wf_dbdc_pins: wf-dbdc-pins {
  343. mux {
  344. function = "wifi";
  345. groups = "wf_dbdc";
  346. };
  347. conf {
  348. pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
  349. "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
  350. "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
  351. "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
  352. "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
  353. "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
  354. "WF1_TOP_CLK", "WF1_TOP_DATA";
  355. drive-strength = <4>;
  356. };
  357. };
  358. };
  359. &spi0 {
  360. pinctrl-names = "default";
  361. pinctrl-0 = <&spi_flash_pins>;
  362. status = "okay";
  363. };
  364. &ssusb {
  365. vusb33-supply = <&reg_3p3v>;
  366. vbus-supply = <&reg_5v>;
  367. status = "okay";
  368. };
  369. &uart0 {
  370. status = "okay";
  371. };
  372. &uart1 {
  373. pinctrl-names = "default";
  374. pinctrl-0 = <&uart1_pins>;
  375. status = "okay";
  376. };
  377. &usb_phy {
  378. status = "okay";
  379. };
  380. &i2c0 {
  381. pinctrl-names = "default";
  382. pinctrl-0 = <&i2c0_pins>;
  383. status = "okay";
  384. };
  385. &pwm {
  386. pinctrl-names = "default";
  387. pinctrl-0 = <&pwm_pins>;
  388. status = "okay";
  389. };
  390. &fan {
  391. pwms = <&pwm 0 10000 0>;
  392. cooling-levels = <255 96 52 0>;
  393. status = "okay";
  394. };
  395. &wmac {
  396. mediatek,eeprom-data = <0x86790900 0xc4326 0x60000000 0x00 0x00 0x00 0x00 0x00
  397. 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
  398. 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x1000000
  399. 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
  400. 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
  401. 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
  402. 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
  403. 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
  404. 0x00 0x800 0x00 0x00 0x00 0x00 0x00 0x00
  405. 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
  406. 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
  407. 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
  408. 0x00 0x00 0x00 0x00 0x24649090 0x280000 0x5100000 0x00
  409. 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
  410. 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
  411. 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
  412. 0x21e00 0x21e0002 0x1e00021e 0x22800 0x2280002 0x28000228 0x00 0x00
  413. 0x00 0x00 0x00 0x00 0x00 0x00 0x8080 0x8080fdf7
  414. 0x903150d 0x80808080 0x80808080 0x5050d0d 0x1313c6c6 0xc3c3c200 0xc200c2 0x8182
  415. 0x8585c2c2 0x82828282 0x858500c2 0xc2000081 0x82858587 0x87c2c200 0x81818285 0x858787c2
  416. 0xc2000081 0x82858587 0x87c2c200 0x818285 0x858787c2 0xc2000081 0x82858587 0x87c4c4c2
  417. 0xc100c300 0xc3c3c100 0x818383c3 0xc3c3c100 0x81838300 0xc2c2c2c0 0x81828484 0xc3
  418. 0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x838686c2 0xc2c2c081 0x82848486 0x86c3c3c3
  419. 0xc1008183 0x838686c3 0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x83868622 0x28002228
  420. 0x222800 0x22280000 0xdddddddd 0xdddddddd 0xddbbbbbb 0xccccccdd 0xdddddddd 0xdddddddd
  421. 0xeeeeeecc 0xccccdddd 0xdddddddd 0x4a5662 0x4a 0x56620000 0x4a5662 0x4a
  422. 0x56620000 0x88888888 0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600
  423. 0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600 0x00 0xf0f0cc00
  424. 0x00 0xaaaa 0xaabbbbbb 0xcccccccc 0xccccbbbb 0xbbbbbbbb 0xbbbbbbaa 0xaaaabbbb
  425. 0xbbaaaaaa 0x999999aa 0xaaaabbbb 0xbbcccccc 0x00 0xaaaa 0xaa000000 0xbbbbbbbb
  426. 0xbbbbaaaa 0xaa999999 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb
  427. 0x00 0x00 0x00 0x99999999 0x9999aaaa 0xaaaaaaaa 0x999999aa 0xaaaaaaaa
  428. 0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb 0x00 0xeeee 0xeeffffff 0xcccccccc
  429. 0xccccdddd 0xddbbbbbb 0xccccccbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbcccc 0xccdddddd
  430. 0x516200 0x686e0051 0x6200686e 0x516200 0x686e0051 0x6200686e 0x516200 0x686e0051
  431. 0x6200686e 0x516200 0x686e0051 0x6200686e 0x516200 0x686e0051 0x6200686e 0x516200
  432. 0x686e0051 0x6200686e 0x516200 0x686e0051 0x6200686e 0x516200 0x686e0051 0x6200686e
  433. 0x516200 0x686e0051 0x6200686e 0x516200 0x686e0051 0x6200686e 0x516200 0x686e0051
  434. 0x6200686e 0x516200 0x686e0051 0x6200686e 0x516200 0x686e0051 0x6200686e 0x516200
  435. 0x686e0051 0x6200686e 0x516200 0x686e0051 0x6200686e 0x516200 0x686e0051 0x6200686e
  436. 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888
  437. 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
  438. 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
  439. 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
  440. 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
  441. 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
  442. 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
  443. 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
  444. 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
  445. 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
  446. 0x00 0x00 0x00 0x00 0x01 0x6000100 0x1050002 0xff0300
  447. 0xf900fe03 0x00 0x00 0x9b 0x6e370000 0x00 0xfc0009 0xa00fe00
  448. 0x60700fe 0x70800 0x5000b0a 0x00 0x00 0xe2 0x96460000 0x00
  449. 0x400f7 0xf8000300 0xfcfe0003 0xfbfc00 0xee00e3f2 0x00 0x00 0x11
  450. 0xbb550000 0x00 0x600f6 0xfc000300 0xfbfe0004 0xfafe00 0xf600ecf2 0x00
  451. 0x00 0x1f 0xbf580000 0x00 0x600f5 0xf6000400 0xf8f90004 0xf7f800
  452. 0xf700f0f4 0x00 0x00 0x24 0xbe570000 0x00 0x800f8 0xfe000600
  453. 0xf8fd0007 0xf9fe00 0xf500f0f4 0x00 0x00 0x2d 0xd6610000 0x00
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  524. };