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737-06-net-ethernet-mtk_eth_soc-add-support-for-MT7988-SoC.patch

737-06-net-ethernet-mtk_eth_soc-add-support-for-MT7988-SoC.patch 17 KB
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  1. From 661bacf4363ca68939c15e20056b5f72fbd034e7 Mon Sep 17 00:00:00 2001
    2. 

  2. From: Lorenzo Bianconi <[email protected]>
    3. 

  3. Date: Sat, 25 Feb 2023 00:08:24 +0100
    4. 

  4. Subject: [PATCH 6/7] net: ethernet: mtk_eth_soc: add support for MT7988 SoC
    5. 

  5. 

  6. Introduce support for ethernet chip available in MT7988 SoC to
    7. 

  7. mtk_eth_soc driver.
    8. 

  8. ---
    9. 

  9.  drivers/net/ethernet/mediatek/mtk_eth_soc.c | 153 ++++++++++++++--
    10. 

  10.  drivers/net/ethernet/mediatek/mtk_eth_soc.h | 193 ++++++++++++++------
    11. 

  11.  2 files changed, 279 insertions(+), 67 deletions(-)
    12. 

  12. 

  13. --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
    14. 

  14. +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
    15. 

  15. @@ -152,6 +152,54 @@ static const struct mtk_reg_map mt7986_r
    16. 

  16.  	.pse_oq_sta		= 0x01a0,
    17. 

  17.  };
    18. 

  18.  
    19. 

  19. +static const struct mtk_reg_map mt7988_reg_map = {
    20. 

  20. +	.tx_irq_mask		= 0x461c,
    21. 

  21. +	.tx_irq_status		= 0x4618,
    22. 

  22. +	.pdma = {
    23. 

  23. +		.rx_ptr		= 0x6900,
    24. 

  24. +		.rx_cnt_cfg	= 0x6904,
    25. 

  25. +		.pcrx_ptr	= 0x6908,
    26. 

  26. +		.glo_cfg	= 0x6a04,
    27. 

  27. +		.rst_idx	= 0x6a08,
    28. 

  28. +		.delay_irq	= 0x6a0c,
    29. 

  29. +		.irq_status	= 0x6a20,
    30. 

  30. +		.irq_mask	= 0x6a28,
    31. 

  31. +		.adma_rx_dbg0	= 0x6a38,
    32. 

  32. +		.int_grp	= 0x6a50,
    33. 

  33. +	},
    34. 

  34. +	.qdma = {
    35. 

  35. +		.qtx_cfg	= 0x4400,
    36. 

  36. +		.qtx_sch	= 0x4404,
    37. 

  37. +		.rx_ptr		= 0x4500,
    38. 

  38. +		.rx_cnt_cfg	= 0x4504,
    39. 

  39. +		.qcrx_ptr	= 0x4508,
    40. 

  40. +		.glo_cfg	= 0x4604,
    41. 

  41. +		.rst_idx	= 0x4608,
    42. 

  42. +		.delay_irq	= 0x460c,
    43. 

  43. +		.fc_th		= 0x4610,
    44. 

  44. +		.int_grp	= 0x4620,
    45. 

  45. +		.hred		= 0x4644,
    46. 

  46. +		.ctx_ptr	= 0x4700,
    47. 

  47. +		.dtx_ptr	= 0x4704,
    48. 

  48. +		.crx_ptr	= 0x4710,
    49. 

  49. +		.drx_ptr	= 0x4714,
    50. 

  50. +		.fq_head	= 0x4720,
    51. 

  51. +		.fq_tail	= 0x4724,
    52. 

  52. +		.fq_count	= 0x4728,
    53. 

  53. +		.fq_blen	= 0x472c,
    54. 

  54. +		.tx_sch_rate	= 0x4798,
    55. 

  55. +	},
    56. 

  56. +	.gdm1_cnt		= 0x1c00,
    57. 

  57. +	.gdma_to_ppe		= 0x3333,
    58. 

  58. +	.ppe_base		= 0x2200,
    59. 

  59. +	.wdma_base = {
    60. 

  60. +		[0]		= 0x4800,
    61. 

  61. +		[1]		= 0x4c00,
    62. 

  62. +	},
    63. 

  63. +	.pse_iq_sta		= 0x0180,
    64. 

  64. +	.pse_oq_sta		= 0x01a0,
    65. 

  65. +};
    66. 

  66. +
    67. 

  67.  /* strings used by ethtool */
    68. 

  68.  static const struct mtk_ethtool_stats {
    69. 

  69.  	char str[ETH_GSTRING_LEN];
    70. 

  70. @@ -179,10 +227,54 @@ static const struct mtk_ethtool_stats {
    71. 

  71.  };
    72. 

  72.  
    73. 

  73.  static const char * const mtk_clks_source_name[] = {
    74. 

  74. -	"ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll",
    75. 

  75. -	"sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb",
    76. 

  76. -	"sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb",
    77. 

  77. -	"sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1"
    78. 

  78. +	"ethif",
    79. 

  79. +	"sgmiitop",
    80. 

  80. +	"esw",
    81. 

  81. +	"gp0",
    82. 

  82. +	"gp1",
    83. 

  83. +	"gp2",
    84. 

  84. +	"gp3",
    85. 

  85. +	"xgp1",
    86. 

  86. +	"xgp2",
    87. 

  87. +	"xgp3",
    88. 

  88. +	"crypto",
    89. 

  89. +	"fe",
    90. 

  90. +	"trgpll",
    91. 

  91. +	"sgmii_tx250m",
    92. 

  92. +	"sgmii_rx250m",
    93. 

  93. +	"sgmii_cdr_ref",
    94. 

  94. +	"sgmii_cdr_fb",
    95. 

  95. +	"sgmii2_tx250m",
    96. 

  96. +	"sgmii2_rx250m",
    97. 

  97. +	"sgmii2_cdr_ref",
    98. 

  98. +	"sgmii2_cdr_fb",
    99. 

  99. +	"sgmii_ck",
    100. 

  100. +	"eth2pll",
    101. 

  101. +	"wocpu0",
    102. 

  102. +	"wocpu1",
    103. 

  103. +	"netsys0",
    104. 

  104. +	"netsys1",
    105. 

  105. +	"ethwarp_wocpu2",
    106. 

  106. +	"ethwarp_wocpu1",
    107. 

  107. +	"ethwarp_wocpu0",
    108. 

  108. +	"top_usxgmii0_sel",
    109. 

  109. +	"top_usxgmii1_sel",
    110. 

  110. +	"top_sgm0_sel",
    111. 

  111. +	"top_sgm1_sel",
    112. 

  112. +	"top_xfi_phy0_xtal_sel",
    113. 

  113. +	"top_xfi_phy1_xtal_sel",
    114. 

  114. +	"top_eth_gmii_sel",
    115. 

  115. +	"top_eth_refck_50m_sel",
    116. 

  116. +	"top_eth_sys_200m_sel",
    117. 

  117. +	"top_eth_sys_sel",
    118. 

  118. +	"top_eth_xgmii_sel",
    119. 

  119. +	"top_eth_mii_sel",
    120. 

  120. +	"top_netsys_sel",
    121. 

  121. +	"top_netsys_500m_sel",
    122. 

  122. +	"top_netsys_pao_2x_sel",
    123. 

  123. +	"top_netsys_sync_250m_sel",
    124. 

  124. +	"top_netsys_ppefb_250m_sel",
    125. 

  125. +	"top_netsys_warp_sel",
    126. 

  126.  };
    127. 

  127.  
    128. 

  128.  void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
    129. 

  129. @@ -1253,10 +1345,19 @@ static void mtk_tx_set_dma_desc_v2(struc
    130. 

  130.  		data |= TX_DMA_LS0;
    131. 

  131.  	WRITE_ONCE(desc->txd3, data);
    132. 

  132.  
    133. 

  133. -	if (mac->id == MTK_GMAC3_ID)
    134. 

  134. -		data = PSE_GDM3_PORT;
    135. 

  135. -	else
    136. 

  136. -		data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */
    137. 

  137. +	 /* set forward port */
    138. 

  138. +	switch (mac->id) {
    139. 

  139. +	case MTK_GMAC1_ID:
    140. 

  140. +		data = PSE_GDM1_PORT << TX_DMA_FPORT_SHIFT_V2;
    141. 

  141. +		break;
    142. 

  142. +	case MTK_GMAC2_ID:
    143. 

  143. +		data = PSE_GDM2_PORT << TX_DMA_FPORT_SHIFT_V2;
    144. 

  144. +		break;
    145. 

  145. +	case MTK_GMAC3_ID:
    146. 

  146. +		data = PSE_GDM3_PORT << TX_DMA_FPORT_SHIFT_V2;
    147. 

  147. +		break;
    148. 

  148. +	}
    149. 

  149. +
    150. 

  150.  	data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
    151. 

  151.  	WRITE_ONCE(desc->txd4, data);
    152. 

  152.  
    153. 

  153. @@ -5010,6 +5111,25 @@ static const struct mtk_soc_data mt7986_
    154. 

  154.  	},
    155. 

  155.  };
    156. 

  156.  
    157. 

  157. +static const struct mtk_soc_data mt7988_data = {
    158. 

  158. +	.reg_map = &mt7988_reg_map,
    159. 

  159. +	.ana_rgc3 = 0x128,
    160. 

  160. +	.caps = MT7988_CAPS,
    161. 

  161. +	.hw_features = MTK_HW_FEATURES,
    162. 

  162. +	.required_clks = MT7988_CLKS_BITMAP,
    163. 

  163. +	.required_pctl = false,
    164. 

  164. +	.num_devs = 3,
    165. 

  165. +	.txrx = {
    166. 

  166. +		.txd_size = sizeof(struct mtk_tx_dma_v2),
    167. 

  167. +		.rxd_size = sizeof(struct mtk_rx_dma_v2),
    168. 

  168. +		.rx_irq_done_mask = MTK_RX_DONE_INT_V2,
    169. 

  169. +		.rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
    170. 

  170. +		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
    171. 

  171. +		.dma_len_offset = 8,
    172. 

  172. +	},
    173. 

  173. +};
    174. 

  174. +
    175. 

  175. +
    176. 

  176.  static const struct mtk_soc_data rt5350_data = {
    177. 

  177.  	.reg_map = &mt7628_reg_map,
    178. 

  178.  	.caps = MT7628_CAPS,
    179. 

  179. @@ -5028,14 +5148,15 @@ static const struct mtk_soc_data rt5350_
    180. 

  180.  };
    181. 

  181.  
    182. 

  182.  const struct of_device_id of_mtk_match[] = {
    183. 

  183. -	{ .compatible = "mediatek,mt2701-eth", .data = &mt2701_data},
    184. 

  184. -	{ .compatible = "mediatek,mt7621-eth", .data = &mt7621_data},
    185. 

  185. -	{ .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
    186. 

  186. -	{ .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
    187. 

  187. -	{ .compatible = "mediatek,mt7629-eth", .data = &mt7629_data},
    188. 

  188. -	{ .compatible = "mediatek,mt7981-eth", .data = &mt7981_data},
    189. 

  189. -	{ .compatible = "mediatek,mt7986-eth", .data = &mt7986_data},
    190. 

  190. -	{ .compatible = "ralink,rt5350-eth", .data = &rt5350_data},
    191. 

  191. +	{ .compatible = "mediatek,mt2701-eth", .data = &mt2701_data },
    192. 

  192. +	{ .compatible = "mediatek,mt7621-eth", .data = &mt7621_data },
    193. 

  193. +	{ .compatible = "mediatek,mt7622-eth", .data = &mt7622_data },
    194. 

  194. +	{ .compatible = "mediatek,mt7623-eth", .data = &mt7623_data },
    195. 

  195. +	{ .compatible = "mediatek,mt7629-eth", .data = &mt7629_data },
    196. 

  196. +	{ .compatible = "mediatek,mt7981-eth", .data = &mt7981_data },
    197. 

  197. +	{ .compatible = "mediatek,mt7986-eth", .data = &mt7986_data },
    198. 

  198. +	{ .compatible = "mediatek,mt7988-eth", .data = &mt7988_data },
    199. 

  199. +	{ .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
    200. 

  200.  	{},
    201. 

  201.  };
    202. 

  202.  MODULE_DEVICE_TABLE(of, of_mtk_match);
    203. 

  203. --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
    204. 

  204. +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
    205. 

  205. @@ -116,7 +116,8 @@
    206. 

  206.  #define MTK_CDMP_EG_CTRL	0x404
    207. 

  207.  
    208. 

  208.  /* GDM Exgress Control Register */
    209. 

  209. -#define MTK_GDMA_FWD_CFG(x)	(0x500 + (x * 0x1000))
    210. 

  210. +#define MTK_GDMA_FWD_CFG(x)	((x == MTK_GMAC3_ID) ?		\
    211. 

  211. +				 0x540 : 0x500 + (x * 0x1000))
    212. 

  212.  #define MTK_GDMA_SPECIAL_TAG	BIT(24)
    213. 

  213.  #define MTK_GDMA_ICS_EN		BIT(22)
    214. 

  214.  #define MTK_GDMA_TCS_EN		BIT(21)
    215. 

  215. @@ -653,6 +654,11 @@ enum mtk_clks_map {
    216. 

  216.  	MTK_CLK_GP0,
    217. 

  217.  	MTK_CLK_GP1,
    218. 

  218.  	MTK_CLK_GP2,
    219. 

  219. +	MTK_CLK_GP3,
    220. 

  220. +	MTK_CLK_XGP1,
    221. 

  221. +	MTK_CLK_XGP2,
    222. 

  222. +	MTK_CLK_XGP3,
    223. 

  223. +	MTK_CLK_CRYPTO,
    224. 

  224.  	MTK_CLK_FE,
    225. 

  225.  	MTK_CLK_TRGPLL,
    226. 

  226.  	MTK_CLK_SGMII_TX_250M,
    227. 

  227. @@ -669,57 +675,108 @@ enum mtk_clks_map {
    228. 

  228.  	MTK_CLK_WOCPU1,
    229. 

  229.  	MTK_CLK_NETSYS0,
    230. 

  230.  	MTK_CLK_NETSYS1,
    231. 

  231. +	MTK_CLK_ETHWARP_WOCPU2,
    232. 

  232. +	MTK_CLK_ETHWARP_WOCPU1,
    233. 

  233. +	MTK_CLK_ETHWARP_WOCPU0,
    234. 

  234. +	MTK_CLK_TOP_USXGMII_SBUS_0_SEL,
    235. 

  235. +	MTK_CLK_TOP_USXGMII_SBUS_1_SEL,
    236. 

  236. +	MTK_CLK_TOP_SGM_0_SEL,
    237. 

  237. +	MTK_CLK_TOP_SGM_1_SEL,
    238. 

  238. +	MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL,
    239. 

  239. +	MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL,
    240. 

  240. +	MTK_CLK_TOP_ETH_GMII_SEL,
    241. 

  241. +	MTK_CLK_TOP_ETH_REFCK_50M_SEL,
    242. 

  242. +	MTK_CLK_TOP_ETH_SYS_200M_SEL,
    243. 

  243. +	MTK_CLK_TOP_ETH_SYS_SEL,
    244. 

  244. +	MTK_CLK_TOP_ETH_XGMII_SEL,
    245. 

  245. +	MTK_CLK_TOP_ETH_MII_SEL,
    246. 

  246. +	MTK_CLK_TOP_NETSYS_SEL,
    247. 

  247. +	MTK_CLK_TOP_NETSYS_500M_SEL,
    248. 

  248. +	MTK_CLK_TOP_NETSYS_PAO_2X_SEL,
    249. 

  249. +	MTK_CLK_TOP_NETSYS_SYNC_250M_SEL,
    250. 

  250. +	MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL,
    251. 

  251. +	MTK_CLK_TOP_NETSYS_WARP_SEL,
    252. 

  252.  	MTK_CLK_MAX
    253. 

  253.  };
    254. 

  254.  
    255. 

  255. -#define MT7623_CLKS_BITMAP	(BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) |  \
    256. 

  256. -				 BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \
    257. 

  257. -				 BIT(MTK_CLK_TRGPLL))
    258. 

  258. -#define MT7622_CLKS_BITMAP	(BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) |  \
    259. 

  259. -				 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
    260. 

  260. -				 BIT(MTK_CLK_GP2) | \
    261. 

  261. -				 BIT(MTK_CLK_SGMII_TX_250M) | \
    262. 

  262. -				 BIT(MTK_CLK_SGMII_RX_250M) | \
    263. 

  263. -				 BIT(MTK_CLK_SGMII_CDR_REF) | \
    264. 

  264. -				 BIT(MTK_CLK_SGMII_CDR_FB) | \
    265. 

  265. -				 BIT(MTK_CLK_SGMII_CK) | \
    266. 

  266. -				 BIT(MTK_CLK_ETH2PLL))
    267. 

  267. +#define MT7623_CLKS_BITMAP	(BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) |  \
    268. 

  268. +				 BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
    269. 

  269. +				 BIT_ULL(MTK_CLK_TRGPLL))
    270. 

  270. +#define MT7622_CLKS_BITMAP	(BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) |  \
    271. 

  271. +				 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
    272. 

  272. +				 BIT_ULL(MTK_CLK_GP2) | \
    273. 

  273. +				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
    274. 

  274. +				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
    275. 

  275. +				 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
    276. 

  276. +				 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
    277. 

  277. +				 BIT_ULL(MTK_CLK_SGMII_CK) | \
    278. 

  278. +				 BIT_ULL(MTK_CLK_ETH2PLL))
    279. 

  279.  #define MT7621_CLKS_BITMAP	(0)
    280. 

  280.  #define MT7628_CLKS_BITMAP	(0)
    281. 

  281. -#define MT7629_CLKS_BITMAP	(BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) |  \
    282. 

  282. -				 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
    283. 

  283. -				 BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \
    284. 

  284. -				 BIT(MTK_CLK_SGMII_TX_250M) | \
    285. 

  285. -				 BIT(MTK_CLK_SGMII_RX_250M) | \
    286. 

  286. -				 BIT(MTK_CLK_SGMII_CDR_REF) | \
    287. 

  287. -				 BIT(MTK_CLK_SGMII_CDR_FB) | \
    288. 

  288. -				 BIT(MTK_CLK_SGMII2_TX_250M) | \
    289. 

  289. -				 BIT(MTK_CLK_SGMII2_RX_250M) | \
    290. 

  290. -				 BIT(MTK_CLK_SGMII2_CDR_REF) | \
    291. 

  291. -				 BIT(MTK_CLK_SGMII2_CDR_FB) | \
    292. 

  292. -				 BIT(MTK_CLK_SGMII_CK) | \
    293. 

  293. -				 BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP))
    294. 

  294. -#define MT7981_CLKS_BITMAP	(BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
    295. 

  295. -				 BIT(MTK_CLK_WOCPU0) | \
    296. 

  296. -				 BIT(MTK_CLK_SGMII_TX_250M) | \
    297. 

  297. -				 BIT(MTK_CLK_SGMII_RX_250M) | \
    298. 

  298. -				 BIT(MTK_CLK_SGMII_CDR_REF) | \
    299. 

  299. -				 BIT(MTK_CLK_SGMII_CDR_FB) | \
    300. 

  300. -				 BIT(MTK_CLK_SGMII2_TX_250M) | \
    301. 

  301. -				 BIT(MTK_CLK_SGMII2_RX_250M) | \
    302. 

  302. -				 BIT(MTK_CLK_SGMII2_CDR_REF) | \
    303. 

  303. -				 BIT(MTK_CLK_SGMII2_CDR_FB) | \
    304. 

  304. -				 BIT(MTK_CLK_SGMII_CK))
    305. 

  305. -#define MT7986_CLKS_BITMAP	(BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
    306. 

  306. -				 BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \
    307. 

  307. -				 BIT(MTK_CLK_SGMII_TX_250M) | \
    308. 

  308. -				 BIT(MTK_CLK_SGMII_RX_250M) | \
    309. 

  309. -				 BIT(MTK_CLK_SGMII_CDR_REF) | \
    310. 

  310. -				 BIT(MTK_CLK_SGMII_CDR_FB) | \
    311. 

  311. -				 BIT(MTK_CLK_SGMII2_TX_250M) | \
    312. 

  312. -				 BIT(MTK_CLK_SGMII2_RX_250M) | \
    313. 

  313. -				 BIT(MTK_CLK_SGMII2_CDR_REF) | \
    314. 

  314. -				 BIT(MTK_CLK_SGMII2_CDR_FB))
    315. 

  315. +#define MT7629_CLKS_BITMAP	(BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) |  \
    316. 

  316. +				 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
    317. 

  317. +				 BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_FE) | \
    318. 

  318. +				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
    319. 

  319. +				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
    320. 

  320. +				 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
    321. 

  321. +				 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
    322. 

  322. +				 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
    323. 

  323. +				 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
    324. 

  324. +				 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
    325. 

  325. +				 BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \
    326. 

  326. +				 BIT_ULL(MTK_CLK_SGMII_CK) | \
    327. 

  327. +				 BIT_ULL(MTK_CLK_ETH2PLL) | BIT_ULL(MTK_CLK_SGMIITOP))
    328. 

  328. +#define MT7981_CLKS_BITMAP	(BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_GP1) | \
    329. 

  329. +				 BIT_ULL(MTK_CLK_WOCPU0) | \
    330. 

  330. +				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
    331. 

  331. +				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
    332. 

  332. +				 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
    333. 

  333. +				 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
    334. 

  334. +				 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
    335. 

  335. +				 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
    336. 

  336. +				 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
    337. 

  337. +				 BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \
    338. 

  338. +				 BIT_ULL(MTK_CLK_SGMII_CK))
    339. 

  339. +#define MT7986_CLKS_BITMAP	(BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_GP1) | \
    340. 

  340. +				 BIT_ULL(MTK_CLK_WOCPU1) | BIT_ULL(MTK_CLK_WOCPU0) | \
    341. 

  341. +				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
    342. 

  342. +				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
    343. 

  343. +				 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
    344. 

  344. +				 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
    345. 

  345. +				 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
    346. 

  346. +				 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
    347. 

  347. +				 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
    348. 

  348. +				 BIT_ULL(MTK_CLK_SGMII2_CDR_FB))
    349. 

  349. +#define MT7988_CLKS_BITMAP	(BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_ESW) | \
    350. 

  350. +				 BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
    351. 

  351. +				 BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \
    352. 

  352. +				 BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \
    353. 

  353. +				 BIT_ULL(MTK_CLK_CRYPTO) | \
    354. 

  354. +				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
    355. 

  355. +				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
    356. 

  356. +				 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
    357. 

  357. +				 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
    358. 

  358. +				 BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \
    359. 

  359. +				 BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \
    360. 

  360. +				 BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \
    361. 

  361. +				 BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \
    362. 

  362. +				 BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \
    363. 

  363. +				 BIT_ULL(MTK_CLK_TOP_SGM_0_SEL) | \
    364. 

  364. +				 BIT_ULL(MTK_CLK_TOP_SGM_1_SEL) | \
    365. 

  365. +				 BIT_ULL(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \
    366. 

  366. +				 BIT_ULL(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \
    367. 

  367. +				 BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \
    368. 

  368. +				 BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \
    369. 

  369. +				 BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \
    370. 

  370. +				 BIT_ULL(MTK_CLK_TOP_ETH_SYS_SEL) | \
    371. 

  371. +				 BIT_ULL(MTK_CLK_TOP_ETH_XGMII_SEL) | \
    372. 

  372. +				 BIT_ULL(MTK_CLK_TOP_ETH_MII_SEL) | \
    373. 

  373. +				 BIT_ULL(MTK_CLK_TOP_NETSYS_SEL) | \
    374. 

  374. +				 BIT_ULL(MTK_CLK_TOP_NETSYS_500M_SEL) | \
    375. 

  375. +				 BIT_ULL(MTK_CLK_TOP_NETSYS_PAO_2X_SEL) | \
    376. 

  376. +				 BIT_ULL(MTK_CLK_TOP_NETSYS_SYNC_250M_SEL) | \
    377. 

  377. +				 BIT_ULL(MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL) | \
    378. 

  378. +				 BIT_ULL(MTK_CLK_TOP_NETSYS_WARP_SEL))
    379. 

  379.  
    380. 

  380.  enum mtk_dev_state {
    381. 

  381.  	MTK_HW_INIT,
    382. 

  382. @@ -847,6 +904,7 @@ enum mkt_eth_capabilities {
    383. 

  383.  	MTK_RGMII_BIT = 0,
    384. 

  384.  	MTK_TRGMII_BIT,
    385. 

  385.  	MTK_SGMII_BIT,
    386. 

  386. +	MTK_USXGMII_BIT,
    387. 

  387.  	MTK_ESW_BIT,
    388. 

  388.  	MTK_GEPHY_BIT,
    389. 

  389.  	MTK_MUX_BIT,
    390. 

  390. @@ -869,6 +927,8 @@ enum mkt_eth_capabilities {
    391. 

  391.  	MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
    392. 

  392.  	MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT,
    393. 

  393.  	MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT,
    394. 

  394. +	MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT,
    395. 

  395. +	MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT,
    396. 

  396.  
    397. 

  397.  	/* PATH BITS */
    398. 

  398.  	MTK_ETH_PATH_GMAC1_RGMII_BIT,
    399. 

  399. @@ -877,13 +937,18 @@ enum mkt_eth_capabilities {
    400. 

  400.  	MTK_ETH_PATH_GMAC2_RGMII_BIT,
    401. 

  401.  	MTK_ETH_PATH_GMAC2_SGMII_BIT,
    402. 

  402.  	MTK_ETH_PATH_GMAC2_GEPHY_BIT,
    403. 

  403. +	MTK_ETH_PATH_GMAC3_SGMII_BIT,
    404. 

  404.  	MTK_ETH_PATH_GDM1_ESW_BIT,
    405. 

  405. +	MTK_ETH_PATH_GMAC1_USXGMII_BIT,
    406. 

  406. +	MTK_ETH_PATH_GMAC2_USXGMII_BIT,
    407. 

  407. +	MTK_ETH_PATH_GMAC3_USXGMII_BIT,
    408. 

  408.  };
    409. 

  409.  
    410. 

  410.  /* Supported hardware group on SoCs */
    411. 

  411.  #define MTK_RGMII		BIT_ULL(MTK_RGMII_BIT)
    412. 

  412.  #define MTK_TRGMII		BIT_ULL(MTK_TRGMII_BIT)
    413. 

  413.  #define MTK_SGMII		BIT_ULL(MTK_SGMII_BIT)
    414. 

  414. +#define MTK_USXGMII		BIT_ULL(MTK_USXGMII_BIT)
    415. 

  415.  #define MTK_ESW			BIT_ULL(MTK_ESW_BIT)
    416. 

  416.  #define MTK_GEPHY		BIT_ULL(MTK_GEPHY_BIT)
    417. 

  417.  #define MTK_MUX			BIT_ULL(MTK_MUX_BIT)
    418. 

  418. @@ -910,6 +975,10 @@ enum mkt_eth_capabilities {
    419. 

  419.  	BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
    420. 

  420.  #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII	\
    421. 

  421.  	BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)
    422. 

  422. +#define MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII	\
    423. 

  423. +	BIT_ULL(MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT)
    424. 

  424. +#define MTK_ETH_MUX_GMAC123_TO_USXGMII	\
    425. 

  425. +	BIT_ULL(MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT)
    426. 

  426.  
    427. 

  427.  /* Supported path present on SoCs */
    428. 

  428.  #define MTK_ETH_PATH_GMAC1_RGMII	BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT)
    429. 

  429. @@ -918,7 +987,11 @@ enum mkt_eth_capabilities {
    430. 

  430.  #define MTK_ETH_PATH_GMAC2_RGMII	BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT)
    431. 

  431.  #define MTK_ETH_PATH_GMAC2_SGMII	BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT)
    432. 

  432.  #define MTK_ETH_PATH_GMAC2_GEPHY	BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
    433. 

  433. +#define MTK_ETH_PATH_GMAC3_SGMII	BIT_ULL(MTK_ETH_PATH_GMAC3_SGMII_BIT)
    434. 

  434.  #define MTK_ETH_PATH_GDM1_ESW		BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT)
    435. 

  435. +#define MTK_ETH_PATH_GMAC1_USXGMII	BIT_ULL(MTK_ETH_PATH_GMAC1_USXGMII_BIT)
    436. 

  436. +#define MTK_ETH_PATH_GMAC2_USXGMII	BIT_ULL(MTK_ETH_PATH_GMAC2_USXGMII_BIT)
    437. 

  437. +#define MTK_ETH_PATH_GMAC3_USXGMII	BIT_ULL(MTK_ETH_PATH_GMAC3_USXGMII_BIT)
    438. 

  438.  
    439. 

  439.  #define MTK_GMAC1_RGMII		(MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
    440. 

  440.  #define MTK_GMAC1_TRGMII	(MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
    441. 

  441. @@ -926,7 +999,11 @@ enum mkt_eth_capabilities {
    442. 

  442.  #define MTK_GMAC2_RGMII		(MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
    443. 

  443.  #define MTK_GMAC2_SGMII		(MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
    444. 

  444.  #define MTK_GMAC2_GEPHY		(MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
    445. 

  445. +#define MTK_GMAC3_SGMII		(MTK_ETH_PATH_GMAC3_SGMII | MTK_SGMII)
    446. 

  446.  #define MTK_GDM1_ESW		(MTK_ETH_PATH_GDM1_ESW | MTK_ESW)
    447. 

  447. +#define MTK_GMAC1_USXGMII	(MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII)
    448. 

  448. +#define MTK_GMAC2_USXGMII	(MTK_ETH_PATH_GMAC2_USXGMII | MTK_USXGMII)
    449. 

  449. +#define MTK_GMAC3_USXGMII	(MTK_ETH_PATH_GMAC3_USXGMII | MTK_USXGMII)
    450. 

  450.  
    451. 

  451.  /* MUXes present on SoCs */
    452. 

  452.  /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
    453. 

  453. @@ -949,6 +1026,12 @@ enum mkt_eth_capabilities {
    454. 

  454.  #define MTK_MUX_GMAC12_TO_GEPHY_SGMII   \
    455. 

  455.  	(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX)
    456. 

  456.  
    457. 

  457. +#define MTK_MUX_GMAC123_TO_GEPHY_SGMII   \
    458. 

  458. +	(MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII | MTK_MUX)
    459. 

  459. +
    460. 

  460. +#define MTK_MUX_GMAC123_TO_USXGMII   \
    461. 

  461. +	(MTK_ETH_MUX_GMAC123_TO_USXGMII | MTK_MUX | MTK_INFRA)
    462. 

  462. +
    463. 

  463.  #ifdef CONFIG_SOC_MT7621
    464. 

  464.  #define MTK_CAP_MASK MTK_NETSYS_V2
    465. 

  465.  #else
    466. 

  466. @@ -987,9 +1070,17 @@ enum mkt_eth_capabilities {
    467. 

  467.  		      MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \
    468. 

  468.  		      MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
    469. 

  469.  
    470. 

  470. -#define MT7986_CAPS  (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
    471. 

  471. -		      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
    472. 

  472. -		      MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
    473. 

  473. +#define MT7986_CAPS  (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII |	\
    474. 

  474. +		      MTK_MUX_GMAC12_TO_GEPHY_SGMII |		\
    475. 

  475. +		      MTK_QDMA | MTK_NETSYS_V2 |		\
    476. 

  476. +		      MTK_RSTCTRL_PPE1)
    477. 

  477. +
    478. 

  478. +#define MT7988_CAPS   (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII |	\
    479. 

  479. +		       MTK_GMAC3_SGMII | MTK_QDMA |		\
    480. 

  480. +		       MTK_MUX_GMAC123_TO_GEPHY_SGMII |		\
    481. 

  481. +		       MTK_NETSYS_V3 | MTK_RSTCTRL_PPE1 |	\
    482. 

  482. +		       MTK_GMAC1_USXGMII | MTK_GMAC2_USXGMII |	\
    483. 

  483. +		       MTK_GMAC3_USXGMII | MTK_MUX_GMAC123_TO_USXGMII)
    484. 

  484.  
    485. 

  485.  struct mtk_tx_dma_desc_info {
    486. 

  486.  	dma_addr_t	addr;
    487. 

  487. @@ -1075,7 +1166,7 @@ struct mtk_soc_data {
    488. 

  488.  	const struct mtk_reg_map *reg_map;
    489. 

  489.  	u32             ana_rgc3;
    490. 

  490.  	u64		caps;
    491. 

  491. -	u32		required_clks;
    492. 

  492. +	u64		required_clks;
    493. 

  493.  	bool		required_pctl;
    494. 

  494.  	u8		offload_version;
    495. 

  495.  	u8		hash_offset;
    496.