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- From c4d621e75e865fa5374946515ad0c5e060b9c446 Mon Sep 17 00:00:00 2001
- From: Leonid Yegoshin <[email protected]>
- Date: Wed, 11 Sep 2013 14:17:47 -0500
- Subject: [PATCH 056/105] MIPS: Fix SMP core calculations when using MT
- support.
- The TCBIND register is only available if the core has MT support. It
- should not be read otherwise. Secondly, the number of TCs (siblings)
- are calculated differently depending on if the kernel is configured
- as SMVP or SMTC.
- Signed-off-by: Leonid Yegoshin <[email protected]>
- Signed-off-by: Steven J. Hill <[email protected]>
- Cc: [email protected]
- Patchwork: https://patchwork.linux-mips.org/patch/5822/
- Signed-off-by: Ralf Baechle <[email protected]>
- (cherry picked from commit 670bac3a8c201fc1f5f92ac6b4a8b42dc8172937)
- ---
- arch/mips/kernel/smp-cmp.c | 13 +++++++++++--
- 1 file changed, 11 insertions(+), 2 deletions(-)
- --- a/arch/mips/kernel/smp-cmp.c
- +++ b/arch/mips/kernel/smp-cmp.c
- @@ -99,7 +99,9 @@ static void cmp_init_secondary(void)
-
- c->core = (read_c0_ebase() >> 1) & 0x1ff;
- #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
- - c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE;
- + if (cpu_has_mipsmt)
- + c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) &
- + TCBIND_CURVPE;
- #endif
- #ifdef CONFIG_MIPS_MT_SMTC
- c->tc_id = (read_c0_tcbind() & TCBIND_CURTC) >> TCBIND_CURTC_SHIFT;
- @@ -177,9 +179,16 @@ void __init cmp_smp_setup(void)
- }
-
- if (cpu_has_mipsmt) {
- - unsigned int nvpe, mvpconf0 = read_c0_mvpconf0();
- + unsigned int nvpe = 1;
- +#ifdef CONFIG_MIPS_MT_SMP
- + unsigned int mvpconf0 = read_c0_mvpconf0();
- +
- + nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
- +#elif defined(CONFIG_MIPS_MT_SMTC)
- + unsigned int mvpconf0 = read_c0_mvpconf0();
-
- nvpe = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
- +#endif
- smp_num_siblings = nvpe;
- }
- pr_info("Detected %i available secondary CPU(s)\n", ncpu);
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