bcm3368.dtsi 2.4 KB

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  1. / {
  2. #address-cells = <1>;
  3. #size-cells = <1>;
  4. compatible = "brcm,bcm3368";
  5. aliases {
  6. pflash = &pflash;
  7. gpio0 = &gpio0;
  8. gpio1 = &gpio1;
  9. serial0 = &uart0;
  10. serial1 = &uart1;
  11. spi0 = &lsspi;
  12. };
  13. cpus {
  14. #address-cells = <1>;
  15. #size-cells = <0>;
  16. cpu@0 {
  17. compatible = "brcm,bmips4350", "mips,mips4Kc";
  18. device_type = "cpu";
  19. reg = <0>;
  20. };
  21. cpu@1 {
  22. compatible = "brcm,bmips4350", "mips,mips4Kc";
  23. device_type = "cpu";
  24. reg = <1>;
  25. };
  26. };
  27. cpu_intc: interrupt-controller {
  28. #address-cells = <0>;
  29. compatible = "mti,cpu-interrupt-controller";
  30. interrupt-controller;
  31. #interrupt-cells = <1>;
  32. };
  33. memory { device_type = "memory"; reg = <0 0>; };
  34. pflash: nor@1e000000 {
  35. compatible = "cfi-flash";
  36. reg = <0x1e000000 0x2000000>;
  37. bank-width = <2>;
  38. #address-cells = <1>;
  39. #size-cells = <1>;
  40. status = "disabled";
  41. };
  42. ubus@fff00000 {
  43. #address-cells = <1>;
  44. #size-cells = <1>;
  45. ranges;
  46. compatible = "simple-bus";
  47. interrupt-parent = <&periph_intc>;
  48. periph_intc: interrupt-controller@fff8c00c {
  49. compatible = "brcm,bcm6345-l1-intc";
  50. reg = <0xfff8c00c 0x8>;
  51. interrupt-controller;
  52. #interrupt-cells = <1>;
  53. interrupt-parent = <&cpu_intc>;
  54. interrupts = <2>;
  55. };
  56. ext_intc0: interrupt-controller@fff8c014 {
  57. compatible = "brcm,bcm6345-ext-intc";
  58. reg = <0xfff8c014 0x4>;
  59. interrupt-controller;
  60. #interrupt-cells = <2>;
  61. interrupts = <25>, <26>, <27>, <28>;
  62. };
  63. gpio1: gpio-controller@fff8c080 {
  64. compatible = "brcm,bcm6345-gpio";
  65. reg = <0xfff8c080 4>, <0xfff8c088 4>;
  66. gpio-controller;
  67. #gpio-cells = <2>;
  68. ngpios = <8>;
  69. };
  70. gpio0: gpio-controller@fff8c084 {
  71. compatible = "brcm,bcm6345-gpio";
  72. reg = <0xfff8c084 4>, <0xfff8c08c 4>;
  73. gpio-controller;
  74. #gpio-cells = <2>;
  75. };
  76. uart0: serial@fff8c100 {
  77. compatible = "brcm,bcm6345-uart";
  78. reg = <0xfff8c100 0x18>;
  79. interrupt-parent = <&periph_intc>;
  80. interrupts = <2>;
  81. /* clocks = <&periph_clk>; */
  82. /* clock-names = "refclk"; */
  83. status = "disabled";
  84. };
  85. uart1: serial@fff8c120 {
  86. compatible = "brcm,bcm6345-uart";
  87. reg = <0xfff8c120 0x18>;
  88. interrupt-parent = <&periph_intc>;
  89. interrupts = <3>;
  90. /* clocks = <&periph_clk>; */
  91. /* clock-names = "refclk"; */
  92. status = "disabled";
  93. };
  94. lsspi: spi@fff8c800 {
  95. #address-cells = <1>;
  96. #size-cells = <0>;
  97. compatible = "brcm,bcm6358-spi";
  98. reg = <0xfff8c800 0x70c>;
  99. interrupts = <1>;
  100. /* clocks = <&clkctl 9>; */
  101. };
  102. };
  103. };