122-05-clk-qcom-clk-krait-generilize-div-functions.patch 4.7 KB

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  1. From 908c361b3c3a139eb3e6a798cb620a6da7514d5c Mon Sep 17 00:00:00 2001
  2. From: Christian Marangi <[email protected]>
  3. Date: Fri, 23 Sep 2022 19:05:39 +0200
  4. Subject: [PATCH 2/4] clk: qcom: clk-krait: generilize div functions
  5. Generilize div functions and remove hardcode to a divisor of 2.
  6. This is just a cleanup and permit to make it more clear the settings of
  7. the devisor when used by the krait-cc driver.
  8. Signed-off-by: Christian Marangi <[email protected]>
  9. ---
  10. drivers/clk/qcom/clk-krait.c | 57 ++++++++++++++++++++----------------
  11. drivers/clk/qcom/clk-krait.h | 11 ++++---
  12. drivers/clk/qcom/krait-cc.c | 7 +++--
  13. 3 files changed, 42 insertions(+), 33 deletions(-)
  14. --- a/drivers/clk/qcom/clk-krait.c
  15. +++ b/drivers/clk/qcom/clk-krait.c
  16. @@ -97,53 +97,58 @@ const struct clk_ops krait_mux_clk_ops =
  17. EXPORT_SYMBOL_GPL(krait_mux_clk_ops);
  18. /* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */
  19. -static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate,
  20. +static long krait_div_round_rate(struct clk_hw *hw, unsigned long rate,
  21. unsigned long *parent_rate)
  22. {
  23. - *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2);
  24. - return DIV_ROUND_UP(*parent_rate, 2);
  25. + struct krait_div_clk *d = to_krait_div_clk(hw);
  26. +
  27. + *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
  28. + rate * d->divisor);
  29. +
  30. + return DIV_ROUND_UP(*parent_rate, d->divisor);
  31. }
  32. -static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
  33. +static int krait_div_set_rate(struct clk_hw *hw, unsigned long rate,
  34. unsigned long parent_rate)
  35. {
  36. - struct krait_div2_clk *d = to_krait_div2_clk(hw);
  37. + struct krait_div_clk *d = to_krait_div_clk(hw);
  38. + u8 div_val = krait_div_to_val(d->divisor);
  39. unsigned long flags;
  40. - u32 val;
  41. - u32 mask = BIT(d->width) - 1;
  42. -
  43. - if (d->lpl)
  44. - mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift;
  45. - else
  46. - mask <<= d->shift;
  47. + u32 regval;
  48. spin_lock_irqsave(&krait_clock_reg_lock, flags);
  49. - val = krait_get_l2_indirect_reg(d->offset);
  50. - val &= ~mask;
  51. - krait_set_l2_indirect_reg(d->offset, val);
  52. + regval = krait_get_l2_indirect_reg(d->offset);
  53. +
  54. + regval &= ~(d->mask << d->shift);
  55. + regval |= (div_val & d->mask) << d->shift;
  56. +
  57. + if (d->lpl) {
  58. + regval &= ~(d->mask << (d->shift + LPL_SHIFT));
  59. + regval |= (div_val & d->mask) << (d->shift + LPL_SHIFT);
  60. + }
  61. +
  62. + krait_set_l2_indirect_reg(d->offset, regval);
  63. spin_unlock_irqrestore(&krait_clock_reg_lock, flags);
  64. return 0;
  65. }
  66. static unsigned long
  67. -krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
  68. +krait_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
  69. {
  70. - struct krait_div2_clk *d = to_krait_div2_clk(hw);
  71. - u32 mask = BIT(d->width) - 1;
  72. + struct krait_div_clk *d = to_krait_div_clk(hw);
  73. u32 div;
  74. div = krait_get_l2_indirect_reg(d->offset);
  75. div >>= d->shift;
  76. - div &= mask;
  77. - div = (div + 1) * 2;
  78. + div &= d->mask;
  79. - return DIV_ROUND_UP(parent_rate, div);
  80. + return DIV_ROUND_UP(parent_rate, krait_val_to_div(div));
  81. }
  82. -const struct clk_ops krait_div2_clk_ops = {
  83. - .round_rate = krait_div2_round_rate,
  84. - .set_rate = krait_div2_set_rate,
  85. - .recalc_rate = krait_div2_recalc_rate,
  86. +const struct clk_ops krait_div_clk_ops = {
  87. + .round_rate = krait_div_round_rate,
  88. + .set_rate = krait_div_set_rate,
  89. + .recalc_rate = krait_div_recalc_rate,
  90. };
  91. -EXPORT_SYMBOL_GPL(krait_div2_clk_ops);
  92. +EXPORT_SYMBOL_GPL(krait_div_clk_ops);
  93. --- a/drivers/clk/qcom/clk-krait.h
  94. +++ b/drivers/clk/qcom/clk-krait.h
  95. @@ -25,17 +25,20 @@ struct krait_mux_clk {
  96. extern const struct clk_ops krait_mux_clk_ops;
  97. -struct krait_div2_clk {
  98. +struct krait_div_clk {
  99. u32 offset;
  100. - u8 width;
  101. + u32 mask;
  102. + u8 divisor;
  103. u32 shift;
  104. bool lpl;
  105. struct clk_hw hw;
  106. };
  107. -#define to_krait_div2_clk(_hw) container_of(_hw, struct krait_div2_clk, hw)
  108. +#define to_krait_div_clk(_hw) container_of(_hw, struct krait_div_clk, hw)
  109. +#define krait_div_to_val(_div) ((_div) / 2) - 1
  110. +#define krait_val_to_div(_val) ((_val) + 1) * 2
  111. -extern const struct clk_ops krait_div2_clk_ops;
  112. +extern const struct clk_ops krait_div_clk_ops;
  113. #endif
  114. --- a/drivers/clk/qcom/krait-cc.c
  115. +++ b/drivers/clk/qcom/krait-cc.c
  116. @@ -86,11 +86,11 @@ static int krait_notifier_register(struc
  117. static struct clk_hw *
  118. krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
  119. {
  120. - struct krait_div2_clk *div;
  121. + struct krait_div_clk *div;
  122. static struct clk_parent_data p_data[1];
  123. struct clk_init_data init = {
  124. .num_parents = ARRAY_SIZE(p_data),
  125. - .ops = &krait_div2_clk_ops,
  126. + .ops = &krait_div_clk_ops,
  127. .flags = CLK_SET_RATE_PARENT,
  128. };
  129. struct clk_hw *clk;
  130. @@ -101,7 +101,8 @@ krait_add_div(struct device *dev, int id
  131. if (!div)
  132. return ERR_PTR(-ENOMEM);
  133. - div->width = 2;
  134. + div->mask = 0x3;
  135. + div->divisor = 2;
  136. div->shift = 6;
  137. div->lpl = id >= 0;
  138. div->offset = offset;