qcom-ipq4019-cm520-79f.dts 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "qcom-ipq4019.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. #include <dt-bindings/leds/common.h>
  6. #include <dt-bindings/soc/qcom,tcsr.h>
  7. / {
  8. model = "MobiPromo CM520-79F";
  9. compatible = "mobipromo,cm520-79f";
  10. aliases {
  11. led-boot = &led_sys;
  12. led-failsafe = &led_sys;
  13. led-running = &led_sys;
  14. led-upgrade = &led_sys;
  15. };
  16. soc {
  17. rng@22000 {
  18. status = "okay";
  19. };
  20. mdio@90000 {
  21. status = "okay";
  22. pinctrl-0 = <&mdio_pins>;
  23. pinctrl-names = "default";
  24. reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
  25. reset-delay-us = <1000>;
  26. };
  27. tcsr@1949000 {
  28. compatible = "qcom,tcsr";
  29. reg = <0x1949000 0x100>;
  30. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  31. };
  32. tcsr@194b000 {
  33. compatible = "qcom,tcsr";
  34. reg = <0x194b000 0x100>;
  35. qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  36. };
  37. ess_tcsr@1953000 {
  38. compatible = "qcom,tcsr";
  39. reg = <0x1953000 0x1000>;
  40. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  41. };
  42. tcsr@1957000 {
  43. compatible = "qcom,tcsr";
  44. reg = <0x1957000 0x100>;
  45. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  46. };
  47. usb2@60f8800 {
  48. status = "okay";
  49. dwc3@6000000 {
  50. #address-cells = <1>;
  51. #size-cells = <0>;
  52. usb2_port1: port@1 {
  53. reg = <1>;
  54. #trigger-source-cells = <0>;
  55. };
  56. };
  57. };
  58. usb3@8af8800 {
  59. status = "okay";
  60. dwc3@8a00000 {
  61. #address-cells = <1>;
  62. #size-cells = <0>;
  63. usb3_port1: port@1 {
  64. reg = <1>;
  65. #trigger-source-cells = <0>;
  66. };
  67. usb3_port2: port@2 {
  68. reg = <2>;
  69. #trigger-source-cells = <0>;
  70. };
  71. };
  72. };
  73. crypto@8e3a000 {
  74. status = "okay";
  75. };
  76. watchdog@b017000 {
  77. status = "okay";
  78. };
  79. };
  80. led_spi {
  81. compatible = "spi-gpio";
  82. #address-cells = <1>;
  83. #size-cells = <0>;
  84. sck-gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
  85. mosi-gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>;
  86. num-chipselects = <0>;
  87. led_gpio: led_gpio@0 {
  88. compatible = "fairchild,74hc595";
  89. reg = <0>;
  90. gpio-controller;
  91. #gpio-cells = <2>;
  92. registers-number = <1>;
  93. spi-max-frequency = <1000000>;
  94. };
  95. };
  96. leds {
  97. compatible = "gpio-leds";
  98. usb {
  99. function = LED_FUNCTION_USB;
  100. color = <LED_COLOR_ID_BLUE>;
  101. gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>;
  102. linux,default-trigger = "usbport";
  103. trigger-sources = <&usb3_port1>, <&usb3_port2>, <&usb2_port1>;
  104. };
  105. led_sys: can {
  106. label = "blue:can";
  107. gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
  108. };
  109. wan {
  110. function = LED_FUNCTION_WAN;
  111. color = <LED_COLOR_ID_BLUE>;
  112. gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
  113. };
  114. lan1 {
  115. label = "blue:lan1";
  116. gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
  117. };
  118. lan2 {
  119. label = "blue:lan2";
  120. gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
  121. };
  122. wlan2g {
  123. label = "blue:wlan2g";
  124. gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
  125. linux,default-trigger = "phy0tpt";
  126. };
  127. wlan5g {
  128. label = "blue:wlan5g";
  129. gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
  130. linux,default-trigger = "phy1tpt";
  131. };
  132. };
  133. keys {
  134. compatible = "gpio-keys";
  135. reset {
  136. label = "reset";
  137. gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
  138. linux,code = <KEY_RESTART>;
  139. };
  140. };
  141. };
  142. &blsp_dma {
  143. status = "okay";
  144. };
  145. &blsp1_uart1 {
  146. status = "okay";
  147. };
  148. &blsp1_uart2 {
  149. status = "okay";
  150. };
  151. &cryptobam {
  152. status = "okay";
  153. };
  154. &nand {
  155. pinctrl-0 = <&nand_pins>;
  156. pinctrl-names = "default";
  157. status = "okay";
  158. nand@0 {
  159. partitions {
  160. compatible = "fixed-partitions";
  161. #address-cells = <1>;
  162. #size-cells = <1>;
  163. partition@0 {
  164. label = "SBL1";
  165. reg = <0x0 0x100000>;
  166. read-only;
  167. };
  168. partition@100000 {
  169. label = "MIBIB";
  170. reg = <0x100000 0x100000>;
  171. read-only;
  172. };
  173. partition@200000 {
  174. label = "BOOTCONFIG";
  175. reg = <0x200000 0x100000>;
  176. };
  177. partition@300000 {
  178. label = "QSEE";
  179. reg = <0x300000 0x100000>;
  180. read-only;
  181. };
  182. partition@400000 {
  183. label = "QSEE_1";
  184. reg = <0x400000 0x100000>;
  185. read-only;
  186. };
  187. partition@500000 {
  188. label = "CDT";
  189. reg = <0x500000 0x80000>;
  190. read-only;
  191. };
  192. partition@580000 {
  193. label = "CDT_1";
  194. reg = <0x580000 0x80000>;
  195. read-only;
  196. };
  197. partition@600000 {
  198. label = "BOOTCONFIG1";
  199. reg = <0x600000 0x80000>;
  200. };
  201. partition@680000 {
  202. label = "APPSBLENV";
  203. reg = <0x680000 0x80000>;
  204. };
  205. partition@700000 {
  206. label = "APPSBL";
  207. reg = <0x700000 0x200000>;
  208. read-only;
  209. };
  210. partition@900000 {
  211. label = "APPSBL_1";
  212. reg = <0x900000 0x200000>;
  213. read-only;
  214. };
  215. art: partition@b00000 {
  216. label = "ART";
  217. reg = <0xb00000 0x80000>;
  218. read-only;
  219. nvmem-layout {
  220. compatible = "fixed-layout";
  221. #address-cells = <1>;
  222. #size-cells = <1>;
  223. precal_art_1000: precal@1000 {
  224. reg = <0x1000 0x2f20>;
  225. };
  226. macaddr_art_1006: macaddr@1006 {
  227. reg = <0x1006 0x6>;
  228. };
  229. precal_art_5000: precal@5000 {
  230. reg = <0x5000 0x2f20>;
  231. };
  232. macaddr_art_5006: macaddr@5006 {
  233. reg = <0x5006 0x6>;
  234. };
  235. };
  236. };
  237. partition@b80000 {
  238. label = "ubi";
  239. reg = <0xb80000 0x7480000>;
  240. };
  241. };
  242. };
  243. };
  244. &qpic_bam {
  245. status = "okay";
  246. };
  247. &tlmm {
  248. mdio_pins: mdio_pinmux {
  249. mux_1 {
  250. pins = "gpio6";
  251. function = "mdio";
  252. bias-pull-up;
  253. };
  254. mux_2 {
  255. pins = "gpio7";
  256. function = "mdc";
  257. bias-pull-up;
  258. };
  259. };
  260. nand_pins: nand_pins {
  261. pullups {
  262. pins = "gpio52", "gpio53", "gpio58",
  263. "gpio59";
  264. function = "qpic";
  265. bias-pull-up;
  266. };
  267. pulldowns {
  268. pins = "gpio54", "gpio55", "gpio56",
  269. "gpio57", "gpio60", "gpio61",
  270. "gpio62", "gpio63", "gpio64",
  271. "gpio65", "gpio66", "gpio67",
  272. "gpio68", "gpio69";
  273. function = "qpic";
  274. bias-pull-down;
  275. };
  276. };
  277. };
  278. &usb3_ss_phy {
  279. status = "okay";
  280. };
  281. &usb3_hs_phy {
  282. status = "okay";
  283. };
  284. &usb2_hs_phy {
  285. status = "okay";
  286. };
  287. &gmac {
  288. status = "okay";
  289. nvmem-cells = <&macaddr_art_1006>;
  290. nvmem-cell-names = "mac-address";
  291. };
  292. &switch {
  293. status = "okay";
  294. };
  295. &swport3 {
  296. status = "okay";
  297. label = "lan2";
  298. };
  299. &swport4 {
  300. status = "okay";
  301. label = "lan1";
  302. };
  303. &swport5 {
  304. status = "okay";
  305. nvmem-cells = <&macaddr_art_5006>;
  306. nvmem-cell-names = "mac-address";
  307. };
  308. &wifi0 {
  309. status = "okay";
  310. nvmem-cell-names = "pre-calibration";
  311. nvmem-cells = <&precal_art_1000>;
  312. qcom,ath10k-calibration-variant = "CM520-79F";
  313. };
  314. &wifi1 {
  315. status = "okay";
  316. nvmem-cell-names = "pre-calibration";
  317. nvmem-cells = <&precal_art_5000>;
  318. qcom,ath10k-calibration-variant = "CM520-79F";
  319. };