qcom-ipq4019-le1.dts 5.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "qcom-ipq4019.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. #include <dt-bindings/leds/common.h>
  6. #include <dt-bindings/soc/qcom,tcsr.h>
  7. / {
  8. model = "YYeTs LE1";
  9. compatible = "yyets,le1";
  10. aliases {
  11. led-boot = &led_usb;
  12. led-failsafe = &led_usb;
  13. led-upgrade = &led_usb;
  14. ethernet0 = &swport5;
  15. ethernet1 = &gmac;
  16. label-mac-device = &gmac;
  17. };
  18. keys {
  19. compatible = "gpio-keys";
  20. reset {
  21. label = "reset";
  22. gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
  23. linux,code = <KEY_RESTART>;
  24. };
  25. };
  26. leds {
  27. compatible = "gpio-leds";
  28. led_usb: usb {
  29. function = LED_FUNCTION_USB;
  30. color = <LED_COLOR_ID_GREEN>;
  31. gpios = <&tlmm 36 GPIO_ACTIVE_LOW>;
  32. linux,default-trigger = "usbport";
  33. trigger-sources = <&usb3_port1>, <&usb3_port2>, <&usb2_port1>;
  34. };
  35. wlan2g {
  36. label = "green:wlan2g";
  37. gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
  38. linux,default-trigger = "phy0tpt";
  39. };
  40. wlan5g {
  41. label = "green:wlan5g";
  42. gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
  43. linux,default-trigger = "phy1tpt";
  44. };
  45. };
  46. soc {
  47. tcsr@1949000 {
  48. compatible = "qcom,tcsr";
  49. reg = <0x1949000 0x100>;
  50. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  51. };
  52. tcsr@194b000 {
  53. compatible = "qcom,tcsr";
  54. reg = <0x194b000 0x100>;
  55. qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  56. };
  57. ess_tcsr@1953000 {
  58. compatible = "qcom,tcsr";
  59. reg = <0x1953000 0x1000>;
  60. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  61. };
  62. tcsr@1957000 {
  63. compatible = "qcom,tcsr";
  64. reg = <0x1957000 0x100>;
  65. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  66. };
  67. };
  68. };
  69. &blsp_dma {
  70. status = "okay";
  71. };
  72. &blsp1_spi1 {
  73. cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
  74. pinctrl-0 = <&spi_0_pins>;
  75. pinctrl-names = "default";
  76. status = "okay";
  77. flash@0 {
  78. compatible = "jedec,spi-nor";
  79. #address-cells = <1>;
  80. #size-cells = <1>;
  81. reg = <0>;
  82. spi-max-frequency = <24000000>;
  83. partitions {
  84. compatible = "fixed-partitions";
  85. #address-cells = <1>;
  86. #size-cells = <1>;
  87. partition@0 {
  88. label = "SBL1";
  89. reg = <0x0 0x40000>;
  90. read-only;
  91. };
  92. partition@40000 {
  93. label = "MIBIB";
  94. reg = <0x40000 0x20000>;
  95. read-only;
  96. };
  97. partition@60000 {
  98. label = "QSEE";
  99. reg = <0x60000 0x60000>;
  100. read-only;
  101. };
  102. partition@c0000 {
  103. label = "CDT";
  104. reg = <0xc0000 0x10000>;
  105. read-only;
  106. };
  107. partition@d0000 {
  108. label = "DDRPARAMS";
  109. reg = <0xd0000 0x10000>;
  110. read-only;
  111. };
  112. partition@e0000 {
  113. label = "APPSBLENV";
  114. reg = <0xe0000 0x10000>;
  115. read-only;
  116. };
  117. partition@f0000 {
  118. label = "APPSBL";
  119. reg = <0xf0000 0x80000>;
  120. read-only;
  121. };
  122. partition@170000 {
  123. label = "ART";
  124. reg = <0x170000 0x10000>;
  125. read-only;
  126. nvmem-layout {
  127. compatible = "fixed-layout";
  128. #address-cells = <1>;
  129. #size-cells = <1>;
  130. precal_art_1000: precal@1000 {
  131. reg = <0x1000 0x2f20>;
  132. };
  133. precal_art_5000: precal@5000 {
  134. reg = <0x5000 0x2f20>;
  135. };
  136. };
  137. };
  138. partition@180000 {
  139. compatible = "denx,fit";
  140. label = "firmware";
  141. reg = <0x180000 0x1e80000>;
  142. };
  143. };
  144. };
  145. };
  146. &blsp1_uart1 {
  147. pinctrl-0 = <&serial_pins>;
  148. pinctrl-names = "default";
  149. status = "okay";
  150. };
  151. &cryptobam {
  152. status = "okay";
  153. };
  154. &crypto {
  155. status = "okay";
  156. };
  157. &gmac {
  158. status = "okay";
  159. };
  160. &mdio {
  161. pinctrl-0 = <&mdio_pins>;
  162. pinctrl-names = "default";
  163. status = "okay";
  164. };
  165. &prng {
  166. status = "okay";
  167. };
  168. &switch {
  169. status = "okay";
  170. };
  171. &swport1 {
  172. status = "okay";
  173. };
  174. &swport2 {
  175. status = "okay";
  176. };
  177. &swport3 {
  178. status = "okay";
  179. };
  180. &swport4 {
  181. status = "okay";
  182. };
  183. &swport5 {
  184. status = "okay";
  185. };
  186. &tlmm {
  187. mdio_pins: mdio_pinmux {
  188. mux_1 {
  189. pins = "gpio6";
  190. function = "mdio";
  191. bias-pull-up;
  192. };
  193. mux_2 {
  194. pins = "gpio7";
  195. function = "mdc";
  196. bias-pull-up;
  197. };
  198. };
  199. serial_pins: serial_pinmux {
  200. mux {
  201. pins = "gpio16", "gpio17";
  202. function = "blsp_uart0";
  203. bias-disable;
  204. };
  205. };
  206. spi_0_pins: spi_0_pinmux {
  207. pinmux {
  208. function = "blsp_spi0";
  209. pins = "gpio13", "gpio14", "gpio15";
  210. drive-strength = <12>;
  211. bias-disable;
  212. };
  213. pinmux_cs {
  214. function = "gpio";
  215. pins = "gpio12";
  216. drive-strength = <2>;
  217. bias-disable;
  218. output-high;
  219. };
  220. };
  221. };
  222. &usb2 {
  223. status = "okay";
  224. dwc3@6000000 {
  225. #address-cells = <1>;
  226. #size-cells = <0>;
  227. usb2_port1: port@1 {
  228. reg = <1>;
  229. #trigger-source-cells = <0>;
  230. };
  231. };
  232. };
  233. &usb2_hs_phy {
  234. status = "okay";
  235. };
  236. &usb3 {
  237. status = "okay";
  238. dwc3@8a00000 {
  239. #address-cells = <1>;
  240. #size-cells = <0>;
  241. usb3_port1: port@1 {
  242. reg = <1>;
  243. #trigger-source-cells = <0>;
  244. };
  245. usb3_port2: port@2 {
  246. reg = <2>;
  247. #trigger-source-cells = <0>;
  248. };
  249. };
  250. };
  251. &usb3_hs_phy {
  252. status = "okay";
  253. };
  254. &usb3_ss_phy {
  255. status = "okay";
  256. };
  257. &watchdog {
  258. status = "okay";
  259. };
  260. &wifi0 {
  261. status = "okay";
  262. nvmem-cells = <&precal_art_1000>;
  263. nvmem-cell-names = "pre-calibration";
  264. qcom,ath10k-calibration-variant = "YYeTs-LE1";
  265. };
  266. &wifi1 {
  267. status = "okay";
  268. nvmem-cells = <&precal_art_5000>;
  269. nvmem-cell-names = "pre-calibration";
  270. qcom,ath10k-calibration-variant = "YYeTs-LE1";
  271. };