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- From bc5e93e0cd22e360eda23859b939280205567580 Mon Sep 17 00:00:00 2001
- From: "Russell King (Oracle)" <[email protected]>
- Date: Wed, 18 May 2022 15:54:42 +0100
- Subject: [PATCH 03/12] net: mtk_eth_soc: add mask and update PCS speed
- definitions
- The PCS speed setting is a two bit field, but it is defined as two
- separate bits. Add a bitfield mask for the speed definitions, an
- use the FIELD_PREP() macro to define each PCS speed.
- Signed-off-by: Russell King (Oracle) <[email protected]>
- Signed-off-by: Jakub Kicinski <[email protected]>
- ---
- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 8 +++++---
- 1 file changed, 5 insertions(+), 3 deletions(-)
- --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
- +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
- @@ -17,6 +17,7 @@
- #include <linux/phylink.h>
- #include <linux/rhashtable.h>
- #include <linux/dim.h>
- +#include <linux/bitfield.h>
- #include "mtk_ppe.h"
-
- #define MTK_QDMA_PAGE_SIZE 2048
- @@ -473,9 +474,10 @@
- #define SGMSYS_SGMII_MODE 0x20
- #define SGMII_IF_MODE_BIT0 BIT(0)
- #define SGMII_SPEED_DUPLEX_AN BIT(1)
- -#define SGMII_SPEED_10 0x0
- -#define SGMII_SPEED_100 BIT(2)
- -#define SGMII_SPEED_1000 BIT(3)
- +#define SGMII_SPEED_MASK GENMASK(3, 2)
- +#define SGMII_SPEED_10 FIELD_PREP(SGMII_SPEED_MASK, 0)
- +#define SGMII_SPEED_100 FIELD_PREP(SGMII_SPEED_MASK, 1)
- +#define SGMII_SPEED_1000 FIELD_PREP(SGMII_SPEED_MASK, 2)
- #define SGMII_DUPLEX_FULL BIT(4)
- #define SGMII_IF_MODE_BIT5 BIT(5)
- #define SGMII_REMOTE_FAULT_DIS BIT(8)
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