qcom-ipq4019-oap100.dts 5.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "qcom-ipq4019.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. #include <dt-bindings/soc/qcom,tcsr.h>
  6. / {
  7. model = "EdgeCore OAP-100";
  8. compatible = "edgecore,oap100";
  9. aliases {
  10. led-boot = &led_system;
  11. led-failsafe = &led_system;
  12. led-running = &led_system;
  13. led-upgrade = &led_system;
  14. };
  15. chosen {
  16. bootargs-append = " root=/dev/ubiblock0_1";
  17. };
  18. soc {
  19. mdio@90000 {
  20. status = "okay";
  21. pinctrl-0 = <&mdio_pins>;
  22. pinctrl-names = "default";
  23. };
  24. ess-psgmii@98000 {
  25. status = "okay";
  26. };
  27. tcsr@1949000 {
  28. compatible = "qcom,tcsr";
  29. reg = <0x1949000 0x100>;
  30. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  31. };
  32. ess_tcsr@1953000 {
  33. compatible = "qcom,tcsr";
  34. reg = <0x1953000 0x1000>;
  35. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  36. };
  37. tcsr@1957000 {
  38. compatible = "qcom,tcsr";
  39. reg = <0x1957000 0x100>;
  40. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  41. };
  42. tcsr@194b000 {
  43. /* select hostmode */
  44. compatible = "qcom,tcsr";
  45. reg = <0x194b000 0x100>;
  46. qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  47. status = "okay";
  48. };
  49. usb2@60f8800 {
  50. status = "okay";
  51. dwc3@6000000 {
  52. #address-cells = <1>;
  53. #size-cells = <0>;
  54. usb2_port1: port@1 {
  55. reg = <1>;
  56. #trigger-source-cells = <0>;
  57. };
  58. };
  59. };
  60. usb3@8af8800 {
  61. status = "okay";
  62. dwc3@8a00000 {
  63. #address-cells = <1>;
  64. #size-cells = <0>;
  65. usb3_port1: port@1 {
  66. reg = <1>;
  67. #trigger-source-cells = <0>;
  68. };
  69. usb3_port2: port@2 {
  70. reg = <2>;
  71. #trigger-source-cells = <0>;
  72. };
  73. };
  74. };
  75. crypto@8e3a000 {
  76. status = "okay";
  77. };
  78. watchdog@b017000 {
  79. status = "okay";
  80. };
  81. ess-switch@c000000 {
  82. status = "okay";
  83. switch_mac_mode = <0x0>; /* mac mode for RGMII RMII */
  84. switch_initvlas = <0x0007c 0x54>; /* port0 status */
  85. switch_lan_bmp = <0x10>;
  86. };
  87. edma@c080000 {
  88. status = "okay";
  89. };
  90. };
  91. key {
  92. compatible = "gpio-keys";
  93. button@1 {
  94. label = "reset";
  95. linux,code = <KEY_RESTART>;
  96. gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
  97. linux,input-type = <1>;
  98. };
  99. };
  100. leds {
  101. compatible = "gpio-leds";
  102. led_system: led_system {
  103. label = "green:system";
  104. gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
  105. };
  106. led_2g {
  107. label = "blue:wlan2g";
  108. gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>;
  109. };
  110. led_5g {
  111. label = "blue:wlan5g";
  112. gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
  113. };
  114. };
  115. gpio_export {
  116. compatible = "gpio-export";
  117. #size-cells = <0>;
  118. usb {
  119. gpio-export,name = "usb-power";
  120. gpio-export,output = <1>;
  121. gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>;
  122. };
  123. poe {
  124. gpio-export,name = "poe-power";
  125. gpio-export,output = <0>;
  126. gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
  127. };
  128. };
  129. };
  130. &tlmm {
  131. serial_0_pins: serial_pinmux {
  132. mux {
  133. pins = "gpio16", "gpio17";
  134. function = "blsp_uart0";
  135. bias-disable;
  136. };
  137. };
  138. spi_0_pins: spi_0_pinmux {
  139. pinmux {
  140. function = "blsp_spi0";
  141. pins = "gpio13", "gpio14", "gpio15";
  142. drive-strength = <12>;
  143. bias-disable;
  144. };
  145. pinmux_cs {
  146. function = "gpio";
  147. pins = "gpio12";
  148. drive-strength = <2>;
  149. bias-disable;
  150. output-high;
  151. };
  152. };
  153. nand_pins: nand_pins {
  154. pullups {
  155. pins = "gpio53", "gpio58", "gpio59";
  156. function = "qpic";
  157. bias-pull-up;
  158. };
  159. pulldowns {
  160. pins = "gpio54", "gpio55", "gpio56",
  161. "gpio57", "gpio60", "gpio61",
  162. "gpio62", "gpio63", "gpio64",
  163. "gpio65", "gpio66", "gpio67",
  164. "gpio68", "gpio69";
  165. function = "qpic";
  166. bias-pull-down;
  167. };
  168. };
  169. mdio_pins: mdio_pinmux {
  170. mux_1 {
  171. pins = "gpio6";
  172. function = "mdio";
  173. bias-pull-up;
  174. };
  175. mux_2 {
  176. pins = "gpio7";
  177. function = "mdc";
  178. bias-pull-up;
  179. };
  180. };
  181. };
  182. &cryptobam {
  183. status = "okay";
  184. };
  185. &blsp1_spi1 {
  186. pinctrl-0 = <&spi_0_pins>;
  187. pinctrl-names = "default";
  188. status = "okay";
  189. cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
  190. flash@0 {
  191. #address-cells = <1>;
  192. #size-cells = <1>;
  193. compatible = "jedec,spi-nor";
  194. reg = <0>;
  195. linux,modalias = "m25p80", "gd25q256";
  196. spi-max-frequency = <24000000>;
  197. partitions {
  198. compatible = "fixed-partitions";
  199. #address-cells = <1>;
  200. #size-cells = <1>;
  201. partition0@0 {
  202. label = "0:SBL1";
  203. reg = <0x00000000 0x00040000>;
  204. read-only;
  205. };
  206. partition1@40000 {
  207. label = "0:MIBIB";
  208. reg = <0x00040000 0x00020000>;
  209. read-only;
  210. };
  211. partition2@60000 {
  212. label = "0:QSEE";
  213. reg = <0x00060000 0x00060000>;
  214. read-only;
  215. };
  216. partition3@c0000 {
  217. label = "0:CDT";
  218. reg = <0x000c0000 0x00010000>;
  219. read-only;
  220. };
  221. partition4@d0000 {
  222. label = "0:DDRPARAMS";
  223. reg = <0x000d0000 0x00010000>;
  224. read-only;
  225. };
  226. partition5@e0000 {
  227. label = "0:APPSBLENV";
  228. reg = <0x000e0000 0x00010000>;
  229. read-only;
  230. };
  231. partition6@f0000 {
  232. label = "0:APPSBL";
  233. reg = <0x000f0000 0x00080000>;
  234. read-only;
  235. };
  236. partition7@170000 {
  237. label = "0:ART";
  238. reg = <0x00170000 0x00010000>;
  239. read-only;
  240. };
  241. };
  242. };
  243. };
  244. &nand {
  245. pinctrl-0 = <&nand_pins>;
  246. pinctrl-names = "default";
  247. status = "okay";
  248. nand@0 {
  249. partitions {
  250. compatible = "fixed-partitions";
  251. #address-cells = <1>;
  252. #size-cells = <1>;
  253. partition@0 {
  254. label = "rootfs";
  255. reg = <0x00000000 0x4000000>;
  256. };
  257. };
  258. };
  259. };
  260. &blsp_dma {
  261. status = "okay";
  262. };
  263. &blsp1_uart1 {
  264. pinctrl-0 = <&serial_0_pins>;
  265. pinctrl-names = "default";
  266. status = "okay";
  267. };
  268. &qpic_bam {
  269. status = "okay";
  270. };
  271. &wifi0 {
  272. status = "okay";
  273. qcom,ath10k-calibration-variant = "Edgecore OAP100";
  274. };
  275. &wifi1 {
  276. status = "okay";
  277. qcom,ath10k-calibration-variant = "Edgecore OAP100";
  278. };
  279. &usb3_ss_phy {
  280. status = "okay";
  281. };
  282. &usb3_hs_phy {
  283. status = "okay";
  284. };
  285. &usb2_hs_phy {
  286. status = "okay";
  287. };