qcom-ipq4019-rtl30vw.dts 6.7 KB

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  1. // SPDX-License-Identifier: ISC
  2. // Copyright (c) 2015, The Linux Foundation. All rights reserved.
  3. // Copyright (c) 2019, Cezary Jackiewicz <[email protected]>.
  4. // Copyright (c) 2020, Pawel Dembicki <[email protected]>.
  5. #include "qcom-ipq4019.dtsi"
  6. #include <dt-bindings/soc/qcom,tcsr.h>
  7. #include <dt-bindings/gpio/gpio.h>
  8. #include <dt-bindings/input/input.h>
  9. / {
  10. model = "Cell C RTL30VW";
  11. compatible = "cellc,rtl30vw";
  12. aliases {
  13. led-boot = &led_power_blue;
  14. led-failsafe = &led_power_red;
  15. led-running = &led_power_blue;
  16. led-upgrade = &led_power_red;
  17. };
  18. chosen {
  19. bootargs-append = "ubi.mtd=ubifs root=/dev/ubiblock0_0 rootfstype=squashfs ro";
  20. };
  21. led_spi {
  22. compatible = "spi-gpio";
  23. #address-cells = <1>;
  24. #size-cells = <0>;
  25. num-chipselects = <1>;
  26. mosi-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
  27. cs-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
  28. sck-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
  29. led_gpio: led_gpio@0 {
  30. compatible = "fairchild,74hc595";
  31. reg = <0>;
  32. gpio-controller;
  33. #gpio-cells = <2>;
  34. registers-number = <2>;
  35. spi-max-frequency = <1000000>;
  36. };
  37. };
  38. leds {
  39. compatible = "gpio-leds";
  40. led_power_blue: power_blue {
  41. gpios = <&led_gpio 0 GPIO_ACTIVE_HIGH>;
  42. label = "blue:power";
  43. default-state = "on";
  44. };
  45. led_power_red: power_red {
  46. gpios = <&led_gpio 1 GPIO_ACTIVE_HIGH>;
  47. label = "red:power";
  48. };
  49. tp28 {
  50. gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
  51. label = "ext:tp28";
  52. default-state = "keep";
  53. };
  54. tp27 {
  55. gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;
  56. label = "ext:tp27";
  57. default-state = "keep";
  58. };
  59. wlan2g {
  60. gpios = <&led_gpio 8 GPIO_ACTIVE_HIGH>;
  61. label = "blue:wlan2g";
  62. linux,default-trigger = "phy0tpt";
  63. };
  64. wlan5g {
  65. gpios = <&led_gpio 9 GPIO_ACTIVE_HIGH>;
  66. label = "blue:wlan5g";
  67. linux,default-trigger = "phy1tpt";
  68. };
  69. wps {
  70. gpios = <&led_gpio 10 GPIO_ACTIVE_HIGH>;
  71. label = "blue:wps";
  72. };
  73. voip {
  74. gpios = <&led_gpio 11 GPIO_ACTIVE_HIGH>;
  75. label = "blue:voip";
  76. };
  77. s1 {
  78. gpios = <&led_gpio 12 GPIO_ACTIVE_HIGH>;
  79. label = "blue:s1";
  80. };
  81. s2 {
  82. gpios = <&led_gpio 13 GPIO_ACTIVE_HIGH>;
  83. label = "blue:s2";
  84. };
  85. s3 {
  86. gpios = <&led_gpio 14 GPIO_ACTIVE_HIGH>;
  87. label = "blue:s3";
  88. };
  89. s4 {
  90. gpios = <&led_gpio 15 GPIO_ACTIVE_HIGH>;
  91. label = "blue:s4";
  92. };
  93. signal {
  94. gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
  95. label = "red:signal";
  96. };
  97. };
  98. keys {
  99. compatible = "gpio-keys";
  100. wps {
  101. label = "wps";
  102. linux,code = <KEY_WPS_BUTTON>;
  103. gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
  104. };
  105. reset {
  106. label = "reset";
  107. linux,code = <KEY_RESTART>;
  108. gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
  109. };
  110. };
  111. soc {
  112. rng@22000 {
  113. status = "okay";
  114. };
  115. mdio@90000 {
  116. status = "okay";
  117. };
  118. ess-psgmii@98000 {
  119. status = "okay";
  120. };
  121. tcsr@1949000 {
  122. compatible = "qcom,tcsr";
  123. reg = <0x1949000 0x100>;
  124. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  125. };
  126. tcsr@194b000 {
  127. /* select hostmode */
  128. compatible = "qcom,tcsr";
  129. reg = <0x194b000 0x100>;
  130. qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  131. status = "okay";
  132. };
  133. ess_tcsr@1953000 {
  134. compatible = "qcom,tcsr";
  135. reg = <0x1953000 0x1000>;
  136. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  137. };
  138. tcsr@1957000 {
  139. compatible = "qcom,tcsr";
  140. reg = <0x1957000 0x100>;
  141. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  142. };
  143. usb2@60f8800 {
  144. status = "okay";
  145. };
  146. usb3@8af8800 {
  147. status = "okay";
  148. };
  149. crypto@8e3a000 {
  150. status = "okay";
  151. };
  152. watchdog@b017000 {
  153. status = "okay";
  154. };
  155. ess-switch@c000000 {
  156. status = "okay";
  157. };
  158. edma@c080000 {
  159. status = "okay";
  160. };
  161. };
  162. };
  163. &blsp_dma {
  164. status = "okay";
  165. };
  166. &blsp1_spi1 {
  167. pinctrl-0 = <&spi_0_pins>;
  168. pinctrl-names = "default";
  169. status = "okay";
  170. cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
  171. flash@0 {
  172. /*"n25q128a11" is required for proper nand recognition in u-boot. */
  173. compatible = "jedec,spi-nor", "n25q128a11";
  174. #address-cells = <1>;
  175. #size-cells = <1>;
  176. reg = <0>;
  177. spi-max-frequency = <24000000>;
  178. partitions {
  179. compatible = "fixed-partitions";
  180. #address-cells = <1>;
  181. #size-cells = <1>;
  182. partition@0 {
  183. label = "0:SBL1";
  184. reg = <0x0 0x40000>;
  185. read-only;
  186. };
  187. partition@40000 {
  188. label = "0:MIBIB";
  189. reg = <0x40000 0x20000>;
  190. read-only;
  191. };
  192. partition@60000 {
  193. label = "0:QSEE";
  194. reg = <0x60000 0x60000>;
  195. read-only;
  196. };
  197. partition@c0000 {
  198. label = "0:CDT";
  199. reg = <0xc0000 0x10000>;
  200. read-only;
  201. };
  202. partition@d0000 {
  203. label = "0:DDRPARAMS";
  204. reg = <0xd0000 0x10000>;
  205. read-only;
  206. };
  207. partition@e0000 {
  208. label = "0:APPSBLENV";
  209. reg = <0xe0000 0x10000>;
  210. read-only;
  211. };
  212. partition@f0000 {
  213. label = "0:APPSBL";
  214. reg = <0xf0000 0x80000>;
  215. read-only;
  216. };
  217. partition@170000 {
  218. label = "0:ART";
  219. reg = <0x170000 0x10000>;
  220. read-only;
  221. };
  222. partition@180000 {
  223. label = "0:BOOTCONFIG";
  224. reg = <0x180000 0x10000>;
  225. read-only;
  226. };
  227. };
  228. };
  229. flash@1 {
  230. /*
  231. * Factory U-boot looks in 0:BOOTCONFIG partition for active
  232. * partitions settings and mangle partition config. So kernel
  233. * /kernel_1 and rootfs/rootfs_1 pairs can be swaped.
  234. * It isn't a problem but we never can be sure where OFW put
  235. * factory images. "spinand,mt29f" value is required for proper
  236. * nand recognition in u-boot.
  237. */
  238. compatible = "spi-nand","spinand,mt29f";
  239. #address-cells = <1>;
  240. #size-cells = <0>;
  241. reg = <1>;
  242. spi-max-frequency = <24000000>;
  243. partitions {
  244. compatible = "fixed-partitions";
  245. #address-cells = <1>;
  246. #size-cells = <1>;
  247. partition@0 {
  248. label = "kernel";
  249. reg = <0x0 0x400000>;
  250. };
  251. partition@400000 {
  252. label = "rootfs";
  253. reg = <0x400000 0x2000000>;
  254. };
  255. partition@2400000 {
  256. label = "kernel_1";
  257. reg = <0x2400000 0x400000>;
  258. };
  259. partition@2800000 {
  260. label = "rootfs_1";
  261. reg = <0x2800000 0x2000000>;
  262. };
  263. partition@4800000 {
  264. label = "ubifs";
  265. reg = <0x4800000 0x3800000>;
  266. };
  267. };
  268. };
  269. };
  270. &blsp1_uart1 {
  271. pinctrl-0 = <&serial_pins>;
  272. pinctrl-names = "default";
  273. status = "okay";
  274. };
  275. &cryptobam {
  276. status = "okay";
  277. };
  278. &tlmm {
  279. serial_pins: serial_pinmux {
  280. mux {
  281. pins = "gpio60", "gpio61";
  282. function = "blsp_uart0";
  283. bias-disable;
  284. };
  285. };
  286. spi_0_pins: spi_0_pinmux {
  287. pinmux {
  288. function = "blsp_spi0";
  289. pins = "gpio55", "gpio56", "gpio57";
  290. drive-strength = <12>;
  291. bias-disable;
  292. };
  293. pinmux_cs {
  294. function = "gpio";
  295. pins = "gpio54", "gpio59";
  296. drive-strength = <2>;
  297. bias-disable;
  298. output-high;
  299. };
  300. };
  301. };
  302. &usb2_hs_phy {
  303. status = "okay";
  304. };
  305. &usb3_ss_phy {
  306. status = "okay";
  307. };
  308. &usb3_hs_phy {
  309. status = "okay";
  310. };
  311. &wifi0 {
  312. status = "okay";
  313. qcom,ath10k-calibration-variant = "cellc,rtl30vw";
  314. };
  315. &wifi1 {
  316. status = "okay";
  317. qcom,ath10k-calibration-variant = "cellc,rtl30vw";
  318. };