304-ath9k-Fix-RTC_DERIVED_CLK-usage.patch 2.0 KB

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  1. From: Miaoqing Pan <[email protected]>
  2. Date: Thu, 6 Nov 2014 10:52:23 +0530
  3. Subject: [PATCH] ath9k: Fix RTC_DERIVED_CLK usage
  4. Based on the reference clock, which could be 25MHz or 40MHz,
  5. AR_RTC_DERIVED_CLK is programmed differently for AR9340 and AR9550.
  6. But, when a chip reset is done, processing the initvals
  7. sets the register back to the default value.
  8. Fix this by moving the code in ath9k_hw_init_pll() to
  9. ar9003_hw_override_ini(). Also, do this override for AR9531.
  10. Cc: [email protected]
  11. Signed-off-by: Miaoqing Pan <[email protected]>
  12. Signed-off-by: Sujith Manoharan <[email protected]>
  13. ---
  14. --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
  15. +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
  16. @@ -664,6 +664,19 @@ static void ar9003_hw_override_ini(struc
  17. ah->enabled_cals |= TX_CL_CAL;
  18. else
  19. ah->enabled_cals &= ~TX_CL_CAL;
  20. +
  21. + if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah)) {
  22. + if (ah->is_clk_25mhz) {
  23. + REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
  24. + REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
  25. + REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
  26. + } else {
  27. + REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
  28. + REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
  29. + REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
  30. + }
  31. + udelay(100);
  32. + }
  33. }
  34. static void ar9003_hw_prog_ini(struct ath_hw *ah,
  35. --- a/drivers/net/wireless/ath/ath9k/hw.c
  36. +++ b/drivers/net/wireless/ath/ath9k/hw.c
  37. @@ -870,19 +870,6 @@ static void ath9k_hw_init_pll(struct ath
  38. udelay(RTC_PLL_SETTLE_DELAY);
  39. REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
  40. -
  41. - if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
  42. - if (ah->is_clk_25mhz) {
  43. - REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
  44. - REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
  45. - REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
  46. - } else {
  47. - REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
  48. - REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
  49. - REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
  50. - }
  51. - udelay(100);
  52. - }
  53. }
  54. static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,