721-net-phy-realtek-rtl8221-allow-to-configure-SERDES-mo.patch 3.5 KB

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  1. From ace6abaa0f9203083fe4c0a6a74da2d96410b625 Mon Sep 17 00:00:00 2001
  2. From: Alexander Couzens <[email protected]>
  3. Date: Sat, 13 Aug 2022 12:49:33 +0200
  4. Subject: [PATCH 01/10] net: phy: realtek: rtl8221: allow to configure SERDES
  5. mode
  6. The rtl8221 supports multiple SERDES modes:
  7. - SGMII
  8. - 2500base-x
  9. - HiSGMII
  10. Further it supports rate adaption on SERDES links to allow
  11. slow ethernet speeds (10/100/1000mbit) to work on 2500base-x/HiSGMII
  12. links without reducing the SERDES speed.
  13. When operating without rate adapters the SERDES link will follow the
  14. ethernet speed.
  15. Signed-off-by: Alexander Couzens <[email protected]>
  16. ---
  17. drivers/net/phy/realtek.c | 48 +++++++++++++++++++++++++++++++++++++++
  18. 1 file changed, 48 insertions(+)
  19. --- a/drivers/net/phy/realtek.c
  20. +++ b/drivers/net/phy/realtek.c
  21. @@ -54,6 +54,15 @@
  22. RTL8201F_ISR_LINK)
  23. #define RTL8201F_IER 0x13
  24. +#define RTL8221B_MMD_SERDES_CTRL MDIO_MMD_VEND1
  25. +#define RTL8221B_MMD_PHY_CTRL MDIO_MMD_VEND2
  26. +#define RTL8221B_SERDES_OPTION 0x697a
  27. +#define RTL8221B_SERDES_OPTION_MODE_MASK GENMASK(5, 0)
  28. +#define RTL8221B_SERDES_OPTION_MODE_2500BASEX_SGMII 0
  29. +#define RTL8221B_SERDES_OPTION_MODE_HISGMII_SGMII 1
  30. +#define RTL8221B_SERDES_OPTION_MODE_2500BASEX 2
  31. +#define RTL8221B_SERDES_OPTION_MODE_HISGMII 3
  32. +
  33. #define RTL8366RB_POWER_SAVE 0x15
  34. #define RTL8366RB_POWER_SAVE_ON BIT(12)
  35. @@ -879,6 +888,48 @@ static irqreturn_t rtl9000a_handle_inter
  36. return IRQ_HANDLED;
  37. }
  38. +static int rtl8221b_config_init(struct phy_device *phydev)
  39. +{
  40. + u16 option_mode;
  41. +
  42. + switch (phydev->interface) {
  43. + case PHY_INTERFACE_MODE_2500BASEX:
  44. + if (!phydev->is_c45) {
  45. + option_mode = RTL8221B_SERDES_OPTION_MODE_2500BASEX;
  46. + break;
  47. + }
  48. + fallthrough;
  49. + case PHY_INTERFACE_MODE_SGMII:
  50. + option_mode = RTL8221B_SERDES_OPTION_MODE_2500BASEX_SGMII;
  51. + break;
  52. + default:
  53. + return 0;
  54. + }
  55. +
  56. + phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL,
  57. + 0x75f3, 0);
  58. +
  59. + phy_modify_mmd_changed(phydev, RTL8221B_MMD_SERDES_CTRL,
  60. + RTL8221B_SERDES_OPTION,
  61. + RTL8221B_SERDES_OPTION_MODE_MASK, option_mode);
  62. + switch (option_mode) {
  63. + case RTL8221B_SERDES_OPTION_MODE_2500BASEX_SGMII:
  64. + case RTL8221B_SERDES_OPTION_MODE_2500BASEX:
  65. + phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6a04, 0x0503);
  66. + phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6f10, 0xd455);
  67. + phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6f11, 0x8020);
  68. + break;
  69. + case RTL8221B_SERDES_OPTION_MODE_HISGMII_SGMII:
  70. + case RTL8221B_SERDES_OPTION_MODE_HISGMII:
  71. + phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6a04, 0x0503);
  72. + phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6f10, 0xd433);
  73. + phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6f11, 0x8020);
  74. + break;
  75. + }
  76. +
  77. + return 0;
  78. +}
  79. +
  80. static struct phy_driver realtek_drvs[] = {
  81. {
  82. PHY_ID_MATCH_EXACT(0x00008201),
  83. @@ -1033,6 +1084,7 @@ static struct phy_driver realtek_drvs[]
  84. PHY_ID_MATCH_EXACT(0x001cc849),
  85. .name = "RTL8221B-VB-CG 2.5Gbps PHY",
  86. .get_features = rtl822x_get_features,
  87. + .config_init = rtl8221b_config_init,
  88. .config_aneg = rtl822x_config_aneg,
  89. .read_status = rtl822x_read_status,
  90. .suspend = genphy_suspend,
  91. @@ -1044,6 +1096,7 @@ static struct phy_driver realtek_drvs[]
  92. .name = "RTL8221B-VM-CG 2.5Gbps PHY",
  93. .get_features = rtl822x_get_features,
  94. .config_aneg = rtl822x_config_aneg,
  95. + .config_init = rtl8221b_config_init,
  96. .read_status = rtl822x_read_status,
  97. .suspend = genphy_suspend,
  98. .resume = rtlgen_resume,