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- From 0133c7af3aa0420778d106cb90db708cfa45f2c6 Mon Sep 17 00:00:00 2001
- From: Kathiravan Thirumoorthy <[email protected]>
- Date: Thu, 14 Sep 2023 12:29:59 +0530
- Subject: [PATCH] arm64: dts: qcom: ipq6018: include the GPLL0 as clock
- provider for mailbox
- While the kernel is booting up, APSS clock / CPU clock will be running
- at 800MHz with GPLL0 as source. Once the cpufreq driver is available,
- APSS PLL will be configured to the rate based on the opp table and the
- source also will be changed to APSS_PLL_EARLY. So allow the mailbox to
- consume the GPLL0, with this inclusion, CPU Freq correctly reports that
- CPU is running at 800MHz rather than 24MHz.
- Signed-off-by: Kathiravan Thirumoorthy <[email protected]>
- Reviewed-by: Konrad Dybcio <[email protected]>
- Link: https://lore.kernel.org/r/[email protected]
- [bjorn: Updated commit message, as requested by Kathiravan]
- Signed-off-by: Bjorn Andersson <[email protected]>
- ---
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
- --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
- +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
- @@ -619,8 +619,8 @@
- compatible = "qcom,ipq6018-apcs-apps-global";
- reg = <0x0 0x0b111000 0x0 0x1000>;
- #clock-cells = <1>;
- - clocks = <&a53pll>, <&xo>;
- - clock-names = "pll", "xo";
- + clocks = <&a53pll>, <&xo>, <&gcc GPLL0>;
- + clock-names = "pll", "xo", "gpll0";
- #mbox-cells = <1>;
- };
-
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