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001-4.15-05-MIPS-BCM63XX-move-the-HSSPI-PLL-HZ-into-its-own-cloc.patch

001-4.15-05-MIPS-BCM63XX-move-the-HSSPI-PLL-HZ-into-its-own-cloc.patch 2.1 KB
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  1. From cb86630379c8f3432c916d62045b5176f17f4123 Mon Sep 17 00:00:00 2001
    2. 

  2. From: Jonas Gorski <[email protected]>
    3. 

  3. Date: Sun, 16 Jul 2017 12:57:21 +0200
    4. 

  4. Subject: [PATCH V2 6/8] MIPS: BCM63XX: move the HSSPI PLL HZ into its own
    5. 

  5.  clock
    6. 

  6. 

  7. Split up the HSSPL clock into rate and a gate clock, to more closely
    8. 

  8. match the actual hardware.
    9. 

  9. 

  10. Reviewed-by: Florian Fainelli <[email protected]>
    11. 

  11. Signed-off-by: Jonas Gorski <[email protected]>
    12. 

  12. ---
    13. 

  13.  arch/mips/bcm63xx/clk.c | 10 ++++++++--
    14. 

  14.  1 file changed, 8 insertions(+), 2 deletions(-)
    15. 

  15. 

  16. --- a/arch/mips/bcm63xx/clk.c
    17. 

  17. +++ b/arch/mips/bcm63xx/clk.c
    18. 

  18. @@ -247,6 +247,10 @@ static struct clk clk_hsspi = {
    19. 

  19.  	.set	= hsspi_set,
    20. 

  20.  };
    21. 

  21.  
    22. 

  22. +/*
    23. 

  23. + * HSSPI PLL
    24. 

  24. + */
    25. 

  25. +static struct clk clk_hsspi_pll;
    26. 

  26.  
    27. 

  27.  /*
    28. 

  28.   * XTM clock
    29. 

  29. @@ -376,6 +380,7 @@ static struct clk_lookup bcm6328_clks[]
    30. 

  30.  	CLKDEV_INIT(NULL, "periph", &clk_periph),
    31. 

  31.  	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
    32. 

  32.  	CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
    33. 

  33. +	CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
    34. 

  34.  	/* gated clocks */
    35. 

  35.  	CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
    36. 

  36.  	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
    37. 

  37. @@ -443,6 +448,7 @@ static struct clk_lookup bcm6362_clks[]
    38. 

  38.  	CLKDEV_INIT(NULL, "periph", &clk_periph),
    39. 

  39.  	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
    40. 

  40.  	CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
    41. 

  41. +	CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
    42. 

  42.  	/* gated clocks */
    43. 

  43.  	CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
    44. 

  44.  	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
    45. 

  45. @@ -477,7 +483,7 @@ static int __init bcm63xx_clk_init(void)
    46. 

  46.  		clkdev_add_table(bcm3368_clks, ARRAY_SIZE(bcm3368_clks));
    47. 

  47.  		break;
    48. 

  48.  	case BCM6328_CPU_ID:
    49. 

  49. -		clk_hsspi.rate = HSSPI_PLL_HZ_6328;
    50. 

  50. +		clk_hsspi_pll.rate = HSSPI_PLL_HZ_6328;
    51. 

  51.  		clkdev_add_table(bcm6328_clks, ARRAY_SIZE(bcm6328_clks));
    52. 

  52.  		break;
    53. 

  53.  	case BCM6338_CPU_ID:
    54. 

  54. @@ -493,7 +499,7 @@ static int __init bcm63xx_clk_init(void)
    55. 

  55.  		clkdev_add_table(bcm6358_clks, ARRAY_SIZE(bcm6358_clks));
    56. 

  56.  		break;
    57. 

  57.  	case BCM6362_CPU_ID:
    58. 

  58. -		clk_hsspi.rate = HSSPI_PLL_HZ_6362;
    59. 

  59. +		clk_hsspi_pll.rate = HSSPI_PLL_HZ_6362;
    60. 

  60.  		clkdev_add_table(bcm6362_clks, ARRAY_SIZE(bcm6362_clks));
    61. 

  61.  		break;
    62. 

  62.  	case BCM6368_CPU_ID:
    63.