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- From 43f3f187e6f62ca40802afe39495c8a3e20b4bfa Mon Sep 17 00:00:00 2001
- From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <[email protected]>
- Date: Mon, 10 Jan 2022 01:50:50 +0100
- Subject: [PATCH] PCI: aardvark: Replace custom PCIE_CORE_INT_* macros with
- PCI_INTERRUPT_*
- MIME-Version: 1.0
- Content-Type: text/plain; charset=UTF-8
- Content-Transfer-Encoding: 8bit
- Header file linux/pci.h defines enum pci_interrupt_pin with corresponding
- PCI_INTERRUPT_* values.
- Signed-off-by: Pali Rohár <[email protected]>
- Signed-off-by: Marek Behún <[email protected]>
- ---
- drivers/pci/controller/pci-aardvark.c | 6 +-----
- 1 file changed, 1 insertion(+), 5 deletions(-)
- --- a/drivers/pci/controller/pci-aardvark.c
- +++ b/drivers/pci/controller/pci-aardvark.c
- @@ -37,10 +37,6 @@
- #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
- #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7)
- #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8)
- -#define PCIE_CORE_INT_A_ASSERT_ENABLE 1
- -#define PCIE_CORE_INT_B_ASSERT_ENABLE 2
- -#define PCIE_CORE_INT_C_ASSERT_ENABLE 3
- -#define PCIE_CORE_INT_D_ASSERT_ENABLE 4
- /* PIO registers base address and register offsets */
- #define PIO_BASE_ADDR 0x4000
- #define PIO_CTRL (PIO_BASE_ADDR + 0x0)
- @@ -968,7 +964,7 @@ static int advk_sw_pci_bridge_init(struc
- bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
-
- /* Support interrupt A for MSI feature */
- - bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE;
- + bridge->conf.intpin = PCI_INTERRUPT_INTA;
-
- /* Aardvark HW provides PCIe Capability structure in version 2 */
- bridge->pcie_conf.cap = cpu_to_le16(2);
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