rtl839x.dtsi 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include <dt-bindings/clock/rtl83xx-clk.h>
  3. /dts-v1/;
  4. #define STRINGIZE(s) #s
  5. #define LAN_LABEL(p, s) STRINGIZE(p ## s)
  6. #define SWITCH_PORT_LABEL(n) LAN_LABEL(lan, n)
  7. #define INTERNAL_PHY(n) \
  8. phy##n: ethernet-phy@##n { \
  9. reg = <##n>; \
  10. compatible = "ethernet-phy-ieee802.3-c22"; \
  11. phy-is-integrated; \
  12. };
  13. #define EXTERNAL_PHY(n) \
  14. phy##n: ethernet-phy@##n { \
  15. reg = <##n>; \
  16. compatible = "ethernet-phy-ieee802.3-c22"; \
  17. };
  18. #define EXTERNAL_SFP_PHY(n) \
  19. phy##n: ethernet-phy@##n { \
  20. compatible = "ethernet-phy-ieee802.3-c22"; \
  21. sfp; \
  22. media = "fibre"; \
  23. reg = <##n>; \
  24. };
  25. #define EXTERNAL_SFP_PHY_FULL(n, s) \
  26. phy##n: ethernet-phy@##n { \
  27. compatible = "ethernet-phy-ieee802.3-c22"; \
  28. sfp = <&sfp##s>; \
  29. reg = <##n>; \
  30. };
  31. #define SWITCH_PORT(n, s, m) \
  32. port@##n { \
  33. reg = <##n>; \
  34. label = SWITCH_PORT_LABEL(s) ; \
  35. phy-handle = <&phy##n>; \
  36. phy-mode = #m ; \
  37. };
  38. #define SWITCH_SFP_PORT(n, s, m) \
  39. port@##n { \
  40. reg = <##n>; \
  41. label = SWITCH_PORT_LABEL(s) ; \
  42. phy-handle = <&phy##n>; \
  43. phy-mode = #m ; \
  44. fixed-link { \
  45. speed = <1000>; \
  46. full-duplex; \
  47. }; \
  48. };
  49. / {
  50. #address-cells = <1>;
  51. #size-cells = <1>;
  52. compatible = "realtek,rtl839x-soc";
  53. osc: oscillator {
  54. compatible = "fixed-clock";
  55. #clock-cells = <0>;
  56. clock-frequency = <25000000>;
  57. };
  58. ccu: clock-controller {
  59. compatible = "realtek,rtl8390-clock";
  60. #clock-cells = <1>;
  61. clocks = <&osc>;
  62. clock-names = "ref_clk";
  63. };
  64. cpus {
  65. #address-cells = <1>;
  66. #size-cells = <0>;
  67. cpu@0 {
  68. compatible = "mips,mips34Kc";
  69. reg = <0>;
  70. clocks = <&ccu CLK_CPU>;
  71. operating-points-v2 = <&cpu_opp_table>;
  72. };
  73. cpu@1 {
  74. compatible = "mips,mips34Kc";
  75. reg = <1>;
  76. clocks = <&ccu CLK_CPU>;
  77. operating-points-v2 = <&cpu_opp_table>;
  78. };
  79. };
  80. cpu_opp_table: opp-table-0 {
  81. compatible = "operating-points-v2";
  82. opp-shared;
  83. opp00 {
  84. opp-hz = /bits/ 64 <425000000>;
  85. };
  86. opp01 {
  87. opp-hz = /bits/ 64 <450000000>;
  88. };
  89. opp02 {
  90. opp-hz = /bits/ 64 <475000000>;
  91. };
  92. opp03 {
  93. opp-hz = /bits/ 64 <500000000>;
  94. };
  95. opp04 {
  96. opp-hz = /bits/ 64 <525000000>;
  97. };
  98. opp05 {
  99. opp-hz = /bits/ 64 <550000000>;
  100. };
  101. opp06 {
  102. opp-hz = /bits/ 64 <575000000>;
  103. };
  104. opp07 {
  105. opp-hz = /bits/ 64 <600000000>;
  106. };
  107. opp08 {
  108. opp-hz = /bits/ 64 <625000000>;
  109. };
  110. opp09 {
  111. opp-hz = /bits/ 64 <650000000>;
  112. };
  113. opp10 {
  114. opp-hz = /bits/ 64 <675000000>;
  115. };
  116. opp11 {
  117. opp-hz = /bits/ 64 <700000000>;
  118. };
  119. opp12 {
  120. opp-hz = /bits/ 64 <725000000>;
  121. };
  122. opp13 {
  123. opp-hz = /bits/ 64 <750000000>;
  124. };
  125. };
  126. aliases {
  127. serial0 = &uart0;
  128. serial1 = &uart1;
  129. };
  130. chosen {
  131. bootargs = "earlycon";
  132. stdout-path = "serial0:115200n8";
  133. };
  134. cpuintc: cpuintc {
  135. compatible = "mti,cpu-interrupt-controller";
  136. #address-cells = <0>;
  137. #interrupt-cells = <1>;
  138. interrupt-controller;
  139. };
  140. soc: soc {
  141. compatible = "simple-bus";
  142. #address-cells = <1>;
  143. #size-cells = <1>;
  144. ranges = <0x0 0x18000000 0x10000>;
  145. intc: interrupt-controller@3000 {
  146. compatible = "realtek,rtl8390-intc", "realtek,rtl-intc";
  147. reg = <0x3000 0x18>, <0x3018 0x18>;
  148. interrupt-controller;
  149. #interrupt-cells = <2>;
  150. interrupt-parent = <&cpuintc>;
  151. interrupts = <2>, <3>, <4>, <5>, <6>;
  152. };
  153. spi0: spi@1200 {
  154. compatible = "realtek,rtl8380-spi";
  155. reg = <0x1200 0x100>;
  156. #address-cells = <1>;
  157. #size-cells = <0>;
  158. };
  159. timer0: timer@3100 {
  160. compatible = "realtek,rtl8390-timer", "realtek,otto-timer";
  161. reg = <0x3100 0x10>, <0x3110 0x10>, <0x3120 0x10>,
  162. <0x3130 0x10>, <0x3140 0x10>;
  163. interrupt-parent = <&intc>;
  164. interrupts = <29 4>, <28 4>, <17 4>, <16 4>, <15 4>;
  165. clocks = <&ccu CLK_LXB>;
  166. };
  167. uart0: uart@2000 {
  168. compatible = "ns16550a";
  169. reg = <0x2000 0x100>;
  170. clocks = <&ccu CLK_LXB>;
  171. interrupt-parent = <&intc>;
  172. interrupts = <31 1>;
  173. reg-io-width = <1>;
  174. reg-shift = <2>;
  175. fifo-size = <1>;
  176. no-loopback-test;
  177. };
  178. uart1: uart@2100 {
  179. pinctrl-names = "default";
  180. pinctrl-0 = <&enable_uart1>;
  181. compatible = "ns16550a";
  182. reg = <0x2100 0x100>;
  183. clocks = <&ccu CLK_LXB>;
  184. interrupt-parent = <&intc>;
  185. interrupts = <30 2>;
  186. reg-io-width = <1>;
  187. reg-shift = <2>;
  188. fifo-size = <1>;
  189. no-loopback-test;
  190. status = "disabled";
  191. };
  192. gpio0: gpio-controller@3500 {
  193. compatible = "realtek,rtl8390-gpio", "realtek,otto-gpio";
  194. reg = <0x3500 0x20>;
  195. gpio-controller;
  196. #gpio-cells = <2>;
  197. ngpios = <24>;
  198. interrupt-controller;
  199. #interrupt-cells = <2>;
  200. interrupt-parent = <&intc>;
  201. interrupts = <23 2>;
  202. };
  203. watchdog0: watchdog@3150 {
  204. compatible = "realtek,rtl8390-wdt";
  205. reg = <0x3150 0xc>;
  206. realtek,reset-mode = "soc";
  207. clocks = <&ccu CLK_LXB>;
  208. timeout-sec = <30>;
  209. interrupt-parent = <&intc>;
  210. interrupt-names = "phase1", "phase2";
  211. interrupts = <19 4>, <18 4>;
  212. };
  213. };
  214. pinmux@1b000004 {
  215. compatible = "pinctrl-single";
  216. reg = <0x1b000004 0x4>;
  217. pinctrl-single,bit-per-mux;
  218. pinctrl-single,register-width = <32>;
  219. pinctrl-single,function-mask = <0x1>;
  220. #pinctrl-cells = <2>;
  221. enable_uart1: pinmux_enable_uart1 {
  222. pinctrl-single,bits = <0x0 0x1 0x3>;
  223. };
  224. disable_jtag: pinmux_disable_jtag {
  225. pinctrl-single,bits = <0x0 0x2 0x3>;
  226. };
  227. };
  228. /* LED_GLB_CTRL */
  229. pinmux@1b0000e4 {
  230. compatible = "pinctrl-single";
  231. reg = <0x1b0000e4 0x4>;
  232. pinctrl-single,bit-per-mux;
  233. pinctrl-single,register-width = <32>;
  234. pinctrl-single,function-mask = <0x1>;
  235. #pinctrl-cells = <2>;
  236. /* enable GPIO 0 */
  237. pinmux_disable_sys_led: disable_sys_led {
  238. pinctrl-single,bits = <0x0 0x0 0x4000>;
  239. };
  240. };
  241. ethernet0: ethernet@1b00a300 {
  242. compatible = "realtek,rtl838x-eth";
  243. reg = <0x1b00a300 0x100>;
  244. interrupt-parent = <&intc>;
  245. interrupts = <24 3>;
  246. phy-mode = "internal";
  247. fixed-link {
  248. speed = <1000>;
  249. full-duplex;
  250. };
  251. };
  252. sram0: sram@9f000000 {
  253. compatible = "mmio-sram";
  254. reg = <0x9f000000 0x18000>;
  255. #address-cells = <1>;
  256. #size-cells = <1>;
  257. ranges = <0 0x9f000000 0x18000>;
  258. };
  259. switch0: switch@1b000000 {
  260. status = "okay";
  261. compatible = "realtek,rtl83xx-switch";
  262. interrupt-parent = <&intc>;
  263. interrupts = <20 2>;
  264. };
  265. };