rtl930x.dtsi 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. /dts-v1/;
  3. / {
  4. #address-cells = <1>;
  5. #size-cells = <1>;
  6. compatible = "realtek,rtl838x-soc";
  7. cpus {
  8. #address-cells = <1>;
  9. #size-cells = <0>;
  10. frequency = <800000000>;
  11. cpu@0 {
  12. compatible = "mips,mips34Kc";
  13. reg = <0>;
  14. };
  15. };
  16. memory@0 {
  17. device_type = "memory";
  18. reg = <0x0 0x8000000>;
  19. };
  20. aliases {
  21. serial0 = &uart0;
  22. serial1 = &uart1;
  23. };
  24. chosen {
  25. bootargs = "earlycon";
  26. stdout-path = "serial0:115200n8";
  27. };
  28. cpuintc: cpuintc {
  29. compatible = "mti,cpu-interrupt-controller";
  30. #address-cells = <0>;
  31. #interrupt-cells = <1>;
  32. interrupt-controller;
  33. };
  34. lx_clk: lx_clk {
  35. compatible = "fixed-clock";
  36. #clock-cells = <0>;
  37. clock-frequency = <175000000>;
  38. };
  39. soc: soc {
  40. compatible = "simple-bus";
  41. #address-cells = <1>;
  42. #size-cells = <1>;
  43. ranges = <0x0 0x18000000 0x10000>;
  44. intc: interrupt-controller@3000 {
  45. compatible = "realtek,rtl9300-intc", "realtek,rtl-intc";
  46. reg = <0x3000 0x18>, <0x3018 0x18>;
  47. interrupt-controller;
  48. #interrupt-cells = <2>;
  49. interrupt-parent = <&cpuintc>;
  50. interrupts = <2>, <3>, <4>, <5>, <6>, <7>;
  51. };
  52. spi0: spi@1200 {
  53. compatible = "realtek,rtl8380-spi";
  54. reg = <0x1200 0x100>;
  55. #address-cells = <1>;
  56. #size-cells = <0>;
  57. };
  58. timer0: timer@3200 {
  59. compatible = "realtek,rtl930x-timer", "realtek,otto-timer";
  60. reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>,
  61. <0x3230 0x10>, <0x3240 0x10>;
  62. interrupt-parent = <&intc>;
  63. interrupts = <7 4>, <8 4>, <9 4>, <10 4>, <11 4>;
  64. clocks = <&lx_clk>;
  65. };
  66. uart0: uart@2000 {
  67. compatible = "ns16550a";
  68. reg = <0x2000 0x100>;
  69. clocks = <&lx_clk>;
  70. interrupt-parent = <&intc>;
  71. interrupts = <30 1>;
  72. reg-io-width = <1>;
  73. reg-shift = <2>;
  74. fifo-size = <1>;
  75. no-loopback-test;
  76. };
  77. uart1: uart@2100 {
  78. compatible = "ns16550a";
  79. reg = <0x2100 0x100>;
  80. clocks = <&lx_clk>;
  81. interrupt-parent = <&intc>;
  82. interrupts = <31 0>;
  83. reg-io-width = <1>;
  84. reg-shift = <2>;
  85. fifo-size = <1>;
  86. no-loopback-test;
  87. status = "disabled";
  88. };
  89. watchdog0: watchdog@3260 {
  90. compatible = "realtek,rtl9300-wdt";
  91. reg = <0x3260 0xc>;
  92. realtek,reset-mode = "soc";
  93. clocks = <&lx_clk>;
  94. timeout-sec = <30>;
  95. interrupt-parent = <&intc>;
  96. interrupt-names = "phase1", "phase2";
  97. interrupts = <5 4>, <6 4>;
  98. };
  99. gpio0: gpio-controller@3300 {
  100. compatible = "realtek,rtl9300-gpio", "realtek,otto-gpio";
  101. reg = <0x3300 0x1c>, <0x3338 0x8>;
  102. gpio-controller;
  103. #gpio-cells = <2>;
  104. ngpios = <24>;
  105. interrupt-controller;
  106. #interrupt-cells = <2>;
  107. interrupt-parent = <&intc>;
  108. interrupts = <13 1>;
  109. };
  110. };
  111. pinmux_led: pinmux@1b00cc00 {
  112. compatible = "pinctrl-single";
  113. reg = <0x1b00cc00 0x4>;
  114. pinctrl-single,bit-per-mux;
  115. pinctrl-single,register-width = <32>;
  116. pinctrl-single,function-mask = <0x1>;
  117. #pinctrl-cells = <2>;
  118. /* enable GPIO 0 */
  119. pinmux_disable_sys_led: disable_sys_led {
  120. pinctrl-single,bits = <0x0 0x0 0x1000>;
  121. };
  122. };
  123. ethernet0: ethernet@1b00a300 {
  124. compatible = "realtek,rtl838x-eth";
  125. reg = <0x1b00a300 0x100>;
  126. interrupt-parent = <&intc>;
  127. interrupts = <24 3>;
  128. phy-mode = "internal";
  129. fixed-link {
  130. speed = <1000>;
  131. full-duplex;
  132. };
  133. };
  134. switch0: switch@1b000000 {
  135. compatible = "realtek,rtl83xx-switch";
  136. status = "okay";
  137. interrupt-parent = <&intc>;
  138. interrupts = <23 2>;
  139. };
  140. };