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- From cf70b726c9844bb5d1ba4bc3c202c5ab3ba4d421 Mon Sep 17 00:00:00 2001
- From: Weijie Gao <[email protected]>
- Date: Fri, 29 Jul 2022 11:15:35 +0800
- Subject: [PATCH 25/31] clk: mediatek: add CLK_XTAL support for clock driver
- This add CLK_XTAL macro and flag to mediatek clock driver common part,
- to make thi SoC that has clock directlly connect to XTAL working.
- Signed-off-by: Weijie Gao <[email protected]>
- ---
- drivers/clk/mediatek/clk-mtk.c | 4 ++++
- drivers/clk/mediatek/clk-mtk.h | 3 ++-
- 2 files changed, 6 insertions(+), 1 deletion(-)
- --- a/drivers/clk/mediatek/clk-mtk.c
- +++ b/drivers/clk/mediatek/clk-mtk.c
- @@ -296,6 +296,7 @@ static ulong mtk_topckgen_get_factor_rat
- rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);
- break;
-
- + case CLK_PARENT_XTAL:
- default:
- rate = priv->tree->xtal_rate;
- }
- @@ -314,6 +315,9 @@ static ulong mtk_infrasys_get_factor_rat
- rate = mtk_clk_find_parent_rate(clk, fdiv->parent,
- priv->parent);
- break;
- + case CLK_PARENT_XTAL:
- + rate = priv->tree->xtal_rate;
- + break;
- default:
- rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);
- }
- --- a/drivers/clk/mediatek/clk-mtk.h
- +++ b/drivers/clk/mediatek/clk-mtk.h
- @@ -29,7 +29,8 @@
- #define CLK_PARENT_APMIXED BIT(4)
- #define CLK_PARENT_TOPCKGEN BIT(5)
- #define CLK_PARENT_INFRASYS BIT(6)
- -#define CLK_PARENT_MASK GENMASK(6, 4)
- +#define CLK_PARENT_XTAL BIT(7)
- +#define CLK_PARENT_MASK GENMASK(7, 4)
-
- #define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34
-
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